[PATCH 0/2][Cosmic][SRU Bionic] hns3: Query firmware for MSIX allocation info

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[PATCH 0/2][Cosmic][SRU Bionic] hns3: Query firmware for MSIX allocation info

dann frazier-4
Clean upstream cherry-picks.

BugLink: https://bugs.launchpad.net/bugs/1793221

Jian Shen (2):
  net: hns3: Fix MSIX allocation issue for VF
  net: hns3: Refine the MSIX allocation for PF

 .../net/ethernet/hisilicon/hns3/hns3_enet.c   |  3 +-
 .../hisilicon/hns3/hns3pf/hclge_cmd.h         |  2 +
 .../hisilicon/hns3/hns3pf/hclge_main.c        |  8 +-
 .../hisilicon/hns3/hns3pf/hclge_main.h        |  3 +-
 .../hisilicon/hns3/hns3vf/hclgevf_cmd.h       | 14 ++++
 .../hisilicon/hns3/hns3vf/hclgevf_main.c      | 80 +++++++++++++++----
 .../hisilicon/hns3/hns3vf/hclgevf_main.h      |  4 +-
 7 files changed, 94 insertions(+), 20 deletions(-)

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2.19.0


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[PATCH 1/2][Cosmic][SRU Bionic] net: hns3: Fix MSIX allocation issue for VF

dann frazier-4
From: Jian Shen <[hidden email]>

BugLink: https://bugs.launchpad.net/bugs/1793221

The msix number for vf is different, depends on the max vf number.
Futherly if the vf supports roce, the offset of msix is not fixed.
It's incorrect to fix the msix number to 33. This patch fixes it by
querying the msix number from firmware, and adjusting it with roce
support.

Fixes: e2cb1dec9779 ("net: hns3: Add HNS3 VF HCL(Hardware Compatibility Layer) Support")
Signed-off-by: Jian Shen <[hidden email]>
Signed-off-by: Peng Li <[hidden email]>
Signed-off-by: Salil Mehta <[hidden email]>
Signed-off-by: David S. Miller <[hidden email]>
(cherry picked from commit 07acf909ee33983fe22334446dd5c2adf0fdca26)
Signed-off-by: dann frazier <[hidden email]>
---
 .../net/ethernet/hisilicon/hns3/hns3_enet.c   |  3 +-
 .../hisilicon/hns3/hns3vf/hclgevf_cmd.h       | 14 ++++
 .../hisilicon/hns3/hns3vf/hclgevf_main.c      | 80 +++++++++++++++----
 .../hisilicon/hns3/hns3vf/hclgevf_main.h      |  4 +-
 4 files changed, 85 insertions(+), 16 deletions(-)

diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
index 3c935b44d8462..0a7891e6361e4 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
@@ -50,7 +50,8 @@ static const struct pci_device_id hns3_pci_tbl[] = {
  {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC),
  HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
  {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0},
- {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 0},
+ {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF),
+ HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
  /* required last entry */
  {0, }
 };
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
index 621c6cbacf767..19b32860309ca 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
@@ -82,6 +82,7 @@ struct hclgevf_cmq {
 enum hclgevf_opcode_type {
  /* Generic command */
  HCLGEVF_OPC_QUERY_FW_VER = 0x0001,
+ HCLGEVF_OPC_QUERY_VF_RSRC = 0x0024,
  /* TQP command */
  HCLGEVF_OPC_QUERY_TX_STATUS = 0x0B03,
  HCLGEVF_OPC_QUERY_RX_STATUS = 0x0B13,
@@ -134,6 +135,19 @@ struct hclgevf_query_version_cmd {
  __le32 firmware_rsv[5];
 };
 
+#define HCLGEVF_MSIX_OFT_ROCEE_S       0
+#define HCLGEVF_MSIX_OFT_ROCEE_M       (0xffff << HCLGEVF_MSIX_OFT_ROCEE_S)
+#define HCLGEVF_VEC_NUM_S              0
+#define HCLGEVF_VEC_NUM_M              (0xff << HCLGEVF_VEC_NUM_S)
+struct hclgevf_query_res_cmd {
+ __le16 tqp_num;
+ __le16 reserved;
+ __le16 msixcap_localid_ba_nic;
+ __le16 msixcap_localid_ba_rocee;
+ __le16 vf_intr_vector_number;
+ __le16 rsv[7];
+};
+
 #define HCLGEVF_RSS_HASH_KEY_OFFSET 4
 #define HCLGEVF_RSS_HASH_KEY_NUM 16
 struct hclgevf_rss_config_cmd {
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
index 4785d23930607..785aa55544cc5 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
@@ -1375,14 +1375,13 @@ static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev)
  struct hnae3_handle *roce = &hdev->roce;
  struct hnae3_handle *nic = &hdev->nic;
 
- roce->rinfo.num_vectors = HCLGEVF_ROCEE_VECTOR_NUM;
+ roce->rinfo.num_vectors = hdev->num_roce_msix;
 
  if (hdev->num_msi_left < roce->rinfo.num_vectors ||
     hdev->num_msi_left == 0)
  return -EINVAL;
 
- roce->rinfo.base_vector =
- hdev->vector_status[hdev->num_msi_used];
+ roce->rinfo.base_vector = hdev->roce_base_vector;
 
  roce->rinfo.netdev = nic->kinfo.netdev;
  roce->rinfo.roce_io_base = hdev->hw.io_base;
@@ -1525,10 +1524,15 @@ static int hclgevf_init_msi(struct hclgevf_dev *hdev)
  if (hclgevf_dev_ongoing_reset(hdev))
  return 0;
 
- hdev->num_msi = HCLGEVF_MAX_VF_VECTOR_NUM;
+ if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B))
+ vectors = pci_alloc_irq_vectors(pdev,
+ hdev->roce_base_msix_offset + 1,
+ hdev->num_msi,
+ PCI_IRQ_MSIX);
+ else
+ vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi,
+ PCI_IRQ_MSI | PCI_IRQ_MSIX);
 
- vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi,
- PCI_IRQ_MSI | PCI_IRQ_MSIX);
  if (vectors < 0) {
  dev_err(&pdev->dev,
  "failed(%d) to allocate MSI/MSI-X vectors\n",
@@ -1543,6 +1547,7 @@ static int hclgevf_init_msi(struct hclgevf_dev *hdev)
  hdev->num_msi = vectors;
  hdev->num_msi_left = vectors;
  hdev->base_msi_vector = pdev->irq;
+ hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset;
 
  hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
    sizeof(u16), GFP_KERNEL);
@@ -1738,6 +1743,45 @@ static void hclgevf_pci_uninit(struct hclgevf_dev *hdev)
  pci_disable_device(pdev);
 }
 
+static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev)
+{
+ struct hclgevf_query_res_cmd *req;
+ struct hclgevf_desc desc;
+ int ret;
+
+ hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true);
+ ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
+ if (ret) {
+ dev_err(&hdev->pdev->dev,
+ "query vf resource failed, ret = %d.\n", ret);
+ return ret;
+ }
+
+ req = (struct hclgevf_query_res_cmd *)desc.data;
+
+ if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) {
+ hdev->roce_base_msix_offset =
+ hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee),
+ HCLGEVF_MSIX_OFT_ROCEE_M,
+ HCLGEVF_MSIX_OFT_ROCEE_S);
+ hdev->num_roce_msix =
+ hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number),
+ HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S);
+
+ /* VF should have NIC vectors and Roce vectors, NIC vectors
+ * are queued before Roce vectors. The offset is fixed to 64.
+ */
+ hdev->num_msi = hdev->num_roce_msix +
+ hdev->roce_base_msix_offset;
+ } else {
+ hdev->num_msi =
+ hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number),
+ HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S);
+ }
+
+ return 0;
+}
+
 static int hclgevf_init_hdev(struct hclgevf_dev *hdev)
 {
  struct pci_dev *pdev = hdev->pdev;
@@ -1755,18 +1799,26 @@ static int hclgevf_init_hdev(struct hclgevf_dev *hdev)
  return ret;
  }
 
+ ret = hclgevf_cmd_init(hdev);
+ if (ret)
+ goto err_cmd_init;
+
+ /* Get vf resource */
+ ret = hclgevf_query_vf_resource(hdev);
+ if (ret) {
+ dev_err(&hdev->pdev->dev,
+ "Query vf status error, ret = %d.\n", ret);
+ goto err_query_vf;
+ }
+
  ret = hclgevf_init_msi(hdev);
  if (ret) {
  dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret);
- goto err_irq_init;
+ goto err_query_vf;
  }
 
  hclgevf_state_init(hdev);
 
- ret = hclgevf_cmd_init(hdev);
- if (ret)
- goto err_cmd_init;
-
  ret = hclgevf_misc_irq_init(hdev);
  if (ret) {
  dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n",
@@ -1822,11 +1874,11 @@ static int hclgevf_init_hdev(struct hclgevf_dev *hdev)
 err_config:
  hclgevf_misc_irq_uninit(hdev);
 err_misc_irq_init:
- hclgevf_cmd_uninit(hdev);
-err_cmd_init:
  hclgevf_state_uninit(hdev);
  hclgevf_uninit_msi(hdev);
-err_irq_init:
+err_query_vf:
+ hclgevf_cmd_uninit(hdev);
+err_cmd_init:
  hclgevf_pci_uninit(hdev);
  return ret;
 }
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h
index 0656e8e5c5f0a..b23ba171473c9 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h
@@ -12,7 +12,6 @@
 #define HCLGEVF_MOD_VERSION "1.0"
 #define HCLGEVF_DRIVER_NAME "hclgevf"
 
-#define HCLGEVF_ROCEE_VECTOR_NUM 0
 #define HCLGEVF_MISC_VECTOR_NUM 0
 
 #define HCLGEVF_INVALID_VPORT 0xffff
@@ -150,6 +149,9 @@ struct hclgevf_dev {
  u16 num_msi;
  u16 num_msi_left;
  u16 num_msi_used;
+ u16 num_roce_msix; /* Num of roce vectors for this VF */
+ u16 roce_base_msix_offset;
+ int roce_base_vector;
  u32 base_msi_vector;
  u16 *vector_status;
  int *vector_irq;
--
2.19.0


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[PATCH 2/2][Cosmic][SRU Bionic] net: hns3: Refine the MSIX allocation for PF

dann frazier-4
In reply to this post by dann frazier-4
From: Jian Shen <[hidden email]>

BugLink: https://bugs.launchpad.net/bugs/1793221

The offset of msix number for roce is different between different
revision id. We should get it from firmware, instead of a fix value.
This patch refines the msix allocation, make it compatible.

Signed-off-by: Jian Shen <[hidden email]>
Signed-off-by: Peng Li <[hidden email]>
Signed-off-by: Salil Mehta <[hidden email]>
Signed-off-by: David S. Miller <[hidden email]>
(cherry picked from commit 375dd5e432128ee071227e3ab0071ca11d01ac8c)
Signed-off-by: dann frazier <[hidden email]>
---
 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h  | 2 ++
 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 8 ++++++--
 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h | 3 +--
 3 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
index 564d54b6e07d7..821d4c2f84bd3 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
@@ -359,6 +359,8 @@ struct hclge_pf_res_cmd {
  __le16 buf_size;
  __le16 msixcap_localid_ba_nic;
  __le16 msixcap_localid_ba_rocee;
+#define HCLGE_MSIX_OFT_ROCEE_S 0
+#define HCLGE_MSIX_OFT_ROCEE_M GENMASK(15, 0)
 #define HCLGE_PF_VEC_NUM_S 0
 #define HCLGE_PF_VEC_NUM_M GENMASK(7, 0)
  __le16 pf_intr_vector_number;
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
index 12eb41e065ee1..2c309dec01f33 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
@@ -933,6 +933,9 @@ static int hclge_query_pf_resource(struct hclge_dev *hdev)
  hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;
 
  if (hnae3_dev_roce_supported(hdev)) {
+ hdev->roce_base_msix_offset =
+ hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee),
+ HCLGE_MSIX_OFT_ROCEE_M, HCLGE_MSIX_OFT_ROCEE_S);
  hdev->num_roce_msi =
  hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number),
  HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
@@ -940,7 +943,8 @@ static int hclge_query_pf_resource(struct hclge_dev *hdev)
  /* PF should have NIC vectors and Roce vectors,
  * NIC vectors are queued before Roce vectors.
  */
- hdev->num_msi = hdev->num_roce_msi  + HCLGE_ROCE_VECTOR_OFFSET;
+ hdev->num_msi = hdev->num_roce_msi  +
+ hdev->roce_base_msix_offset;
  } else {
  hdev->num_msi =
  hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number),
@@ -2038,7 +2042,7 @@ static int hclge_init_msi(struct hclge_dev *hdev)
  hdev->num_msi_left = vectors;
  hdev->base_msi_vector = pdev->irq;
  hdev->roce_base_vector = hdev->base_msi_vector +
- HCLGE_ROCE_VECTOR_OFFSET;
+ hdev->roce_base_msix_offset;
 
  hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
    sizeof(u16), GFP_KERNEL);
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
index dfa5c9456d229..1528fb3fa6be6 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
@@ -16,8 +16,6 @@
 
 #define HCLGE_INVALID_VPORT 0xffff
 
-#define HCLGE_ROCE_VECTOR_OFFSET 96
-
 #define HCLGE_PF_CFG_BLOCK_SIZE 32
 #define HCLGE_PF_CFG_DESC_NUM \
  (HCLGE_PF_CFG_BLOCK_SIZE / HCLGE_CFG_RD_LEN_BYTES)
@@ -509,6 +507,7 @@ struct hclge_dev {
  u16 num_msi;
  u16 num_msi_left;
  u16 num_msi_used;
+ u16 roce_base_msix_offset;
  u32 base_msi_vector;
  u16 *vector_status;
  int *vector_irq;
--
2.19.0


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ACK / APPLIED[C]: [PATCH 0/2][Cosmic][SRU Bionic] hns3: Query firmware for MSIX allocation info

Seth Forshee
In reply to this post by dann frazier-4
On Wed, Sep 19, 2018 at 12:23:17PM -0600, dann frazier wrote:
> Clean upstream cherry-picks.
>
> BugLink: https://bugs.launchpad.net/bugs/1793221

Acked-by: Seth Forshee <[hidden email]>

Applied to cosmic/master-next, thanks!

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ACK: [PATCH 0/2][Cosmic][SRU Bionic] hns3: Query firmware for MSIX allocation info

Kleber Souza
In reply to this post by dann frazier-4
On 09/19/18 20:23, dann frazier wrote:

> Clean upstream cherry-picks.
>
> BugLink: https://bugs.launchpad.net/bugs/1793221
>
> Jian Shen (2):
>   net: hns3: Fix MSIX allocation issue for VF
>   net: hns3: Refine the MSIX allocation for PF
>
>  .../net/ethernet/hisilicon/hns3/hns3_enet.c   |  3 +-
>  .../hisilicon/hns3/hns3pf/hclge_cmd.h         |  2 +
>  .../hisilicon/hns3/hns3pf/hclge_main.c        |  8 +-
>  .../hisilicon/hns3/hns3pf/hclge_main.h        |  3 +-
>  .../hisilicon/hns3/hns3vf/hclgevf_cmd.h       | 14 ++++
>  .../hisilicon/hns3/hns3vf/hclgevf_main.c      | 80 +++++++++++++++----
>  .../hisilicon/hns3/hns3vf/hclgevf_main.h      |  4 +-
>  7 files changed, 94 insertions(+), 20 deletions(-)
>

Acked-by: Kleber Sacilotto de Souza <[hidden email]>

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APPLIED[B]: [PATCH 0/2][Cosmic][SRU Bionic] hns3: Query firmware for MSIX allocation info

Stefan Bader-2
In reply to this post by dann frazier-4
On 19.09.2018 20:23, dann frazier wrote:

> Clean upstream cherry-picks.
>
> BugLink: https://bugs.launchpad.net/bugs/1793221
>
> Jian Shen (2):
>   net: hns3: Fix MSIX allocation issue for VF
>   net: hns3: Refine the MSIX allocation for PF
>
>  .../net/ethernet/hisilicon/hns3/hns3_enet.c   |  3 +-
>  .../hisilicon/hns3/hns3pf/hclge_cmd.h         |  2 +
>  .../hisilicon/hns3/hns3pf/hclge_main.c        |  8 +-
>  .../hisilicon/hns3/hns3pf/hclge_main.h        |  3 +-
>  .../hisilicon/hns3/hns3vf/hclgevf_cmd.h       | 14 ++++
>  .../hisilicon/hns3/hns3vf/hclgevf_main.c      | 80 +++++++++++++++----
>  .../hisilicon/hns3/hns3vf/hclgevf_main.h      |  4 +-
>  7 files changed, 94 insertions(+), 20 deletions(-)
>
Applied to bionic/master-next. Thanks.

-Stefan


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