[PATCH 0/2][F/G/U/OEM-5.10] UBUNTU: SAUCE: Fix the video can't output through WD19TB connected on TGL's Type-C port during cold-boot

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[PATCH 0/2][F/G/U/OEM-5.10] UBUNTU: SAUCE: Fix the video can't output through WD19TB connected on TGL's Type-C port during cold-boot

Koba Ko
BugLink: https://bugs.launchpad.net/bugs/1913372

[Impact]
WD19TB would report the number of lane(2-lane) and it works well on Type-C port
of TGL platform. Change the LTTPR mode to non-transparent mode, WD19TB would
report the larger number of lane(4-lane). It's over the type-c port's bandwidth.

[Fix]
The patch is provided by Imre(https://patchwork.freedesktop.org/series/86267/).
Calculate the PBN divider value based on the rate and lane count link parameters
that the driver uses for all other computation.

[Test Case]
1. Connected the WD19TB with the TGL platform's Type-C port and
connected the external monitor on WD19TB with HDMI/Displayport.
2. Cold boot the TGL platform.
3. Check the monitor can be blinked and the video can output to the monitor.

[Where problems could occur]
It's correct to calculate the PBN divider based on the source's rate
and lane count, not the mst's capability.

Imre Deak (2):
  drm/dp/mst: Export drm_dp_get_vc_payload_bw()
  drm/i915: Fix the MST PBN divider calculation

 drivers/gpu/drm/drm_dp_mst_topology.c       | 24 +++++++++++++++------
 drivers/gpu/drm/i915/display/intel_dp_mst.c |  4 +++-
 include/drm/drm_dp_mst_helper.h             |  1 +
 3 files changed, 22 insertions(+), 7 deletions(-)

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2.25.1


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[PATCH 1/2][F/G/U/OEM-5.10] UBUNTU: SAUCE: drm/dp/mst: Export drm_dp_get_vc_payload_bw()

Koba Ko
From: Imre Deak <[hidden email]>

BugLink: https://bugs.launchpad.net/bugs/1913372

This function will be needed by the next patch where the driver
calculates the BW based on driver specific parameters, so export it.

At the same time sanitize the function params, passing the more natural
link rate instead of the encoding of the same rate.

Cc: Lyude Paul <[hidden email]>
Cc: Ville Syrjala <[hidden email]>
Cc: <[hidden email]>
Cc: [hidden email]
Signed-off-by: Imre Deak <[hidden email]>
Reviewed-by: Lyude Paul <[hidden email]>
Reference: https://patchwork.freedesktop.org/series/86267/
Signed-off-by: Koba Ko <[hidden email]>
---
 drivers/gpu/drm/drm_dp_mst_topology.c | 24 ++++++++++++++++++------
 include/drm/drm_dp_mst_helper.h       |  1 +
 2 files changed, 19 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c
index e87542533640..ae6bc2093479 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -3629,14 +3629,26 @@ static int drm_dp_send_up_ack_reply(struct drm_dp_mst_topology_mgr *mgr,
  return 0;
 }
 
-static int drm_dp_get_vc_payload_bw(u8 dp_link_bw, u8  dp_link_count)
+/**
+ * drm_dp_get_vc_payload_bw - get the VC payload BW for an MST link
+ * @rate: link rate in 10kbits/s units
+ * @lane_count: lane count
+ *
+ * Calculate the toal bandwidth of a MultiStream Transport link. The returned
+ * value is in units of PBNs/(timeslots/1 MTP). This value can be used to
+ * convert the number of PBNs required for a given stream to the number of
+ * timeslots this stream requires in each MTP.
+ */
+int drm_dp_get_vc_payload_bw(int link_rate, int link_lane_count)
 {
- if (dp_link_bw == 0 || dp_link_count == 0)
- DRM_DEBUG_KMS("invalid link bandwidth in DPCD: %x (link count: %d)\n",
-      dp_link_bw, dp_link_count);
+ if (link_rate == 0 || link_lane_count == 0)
+ DRM_DEBUG_KMS("invalid link rate/lane count: (%d / %d)\n",
+      link_rate, link_lane_count);
 
- return dp_link_bw * dp_link_count / 2;
+ /* See DP v2.0 2.6.4.2, VCPayload_Bandwidth_for_OneTimeSlotPer_MTP_Allocation */
+ return link_rate * link_lane_count / 54000;
 }
+EXPORT_SYMBOL(drm_dp_get_vc_payload_bw);
 
 /**
  * drm_dp_read_mst_cap() - check whether or not a sink supports MST
@@ -3692,7 +3704,7 @@ int drm_dp_mst_topology_mgr_set_mst(struct drm_dp_mst_topology_mgr *mgr, bool ms
  goto out_unlock;
  }
 
- mgr->pbn_div = drm_dp_get_vc_payload_bw(mgr->dpcd[1],
+ mgr->pbn_div = drm_dp_get_vc_payload_bw(drm_dp_bw_code_to_link_rate(mgr->dpcd[1]),
  mgr->dpcd[2] & DP_MAX_LANE_COUNT_MASK);
  if (mgr->pbn_div == 0) {
  ret = -EINVAL;
diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h
index f5e92fe9151c..bd1c39907b92 100644
--- a/include/drm/drm_dp_mst_helper.h
+++ b/include/drm/drm_dp_mst_helper.h
@@ -783,6 +783,7 @@ drm_dp_mst_detect_port(struct drm_connector *connector,
 
 struct edid *drm_dp_mst_get_edid(struct drm_connector *connector, struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port);
 
+int drm_dp_get_vc_payload_bw(int link_rate, int link_lane_count);
 
 int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc);
 
--
2.25.1


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[PATCH 2/2][F/G/U/OEM-5.10] UBUNTU: SAUCE: drm/i915: Fix the MST PBN divider calculation

Koba Ko
In reply to this post by Koba Ko
From: Imre Deak <[hidden email]>

BugLink: https://bugs.launchpad.net/bugs/1913372                                 

Atm the driver will calculate a wrong MST timeslots/MTP (aka time unit)
value for MST streams if the link parameters (link rate or lane count)
are limited in a way independent of the sink capabilities (reported by
DPCD).

One example of such a limitation is when a MUX between the sink and
source connects only a limited number of lanes to the display and
connects the rest of the lanes to other peripherals (USB).

Another issue is that atm MST core calculates the divider based on the
backwards compatible DPCD (at address 0x0000) vs. the extended
capability info (at address 0x2200). This can result in leaving some
part of the MST BW unused (For instance in case of the WD19TB dock).

Fix the above two issues by calculating the PBN divider value based on
the rate and lane count link parameters that the driver uses for all
other computation.

Bugzilla: https://gitlab.freedesktop.org/drm/intel/-/issues/2977
Cc: Lyude Paul <[hidden email]>
Cc: Ville Syrjala <[hidden email]>
Cc: <[hidden email]>
Signed-off-by: Imre Deak <[hidden email]>
Reference: https://patchwork.freedesktop.org/series/86267/                       
Signed-off-by: Koba Ko <[hidden email]>
---
 drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 06a490f1e8cc..5f79d6756ccc 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -68,7 +68,9 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
 
  slots = drm_dp_atomic_find_vcpi_slots(state, &intel_dp->mst_mgr,
       connector->port,
-      crtc_state->pbn, 0);
+      crtc_state->pbn,
+      drm_dp_get_vc_payload_bw(crtc_state->port_clock,
+       crtc_state->lane_count));
  if (slots == -EDEADLK)
  return slots;
  if (slots >= 0)
--
2.25.1


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Re: [PATCH 0/2][F/G] UBUNTU: SAUCE: Fix the video can't output through WD19TB connected on TGL's Type-C port during cold-boot

Stefan Bader-2
In reply to this post by Koba Ko
On 27.01.21 07:10, Koba Ko wrote:

> BugLink: https://bugs.launchpad.net/bugs/1913372
>
> [Impact]
> WD19TB would report the number of lane(2-lane) and it works well on Type-C port
> of TGL platform. Change the LTTPR mode to non-transparent mode, WD19TB would
> report the larger number of lane(4-lane). It's over the type-c port's bandwidth.
>
> [Fix]
> The patch is provided by Imre(https://patchwork.freedesktop.org/series/86267/).
> Calculate the PBN divider value based on the rate and lane count link parameters
> that the driver uses for all other computation.
>
> [Test Case]
> 1. Connected the WD19TB with the TGL platform's Type-C port and
> connected the external monitor on WD19TB with HDMI/Displayport.
> 2. Cold boot the TGL platform.
> 3. Check the monitor can be blinked and the video can output to the monitor.
>
> [Where problems could occur]
> It's correct to calculate the PBN divider based on the source's rate
> and lane count, not the mst's capability.
>
> Imre Deak (2):
>   drm/dp/mst: Export drm_dp_get_vc_payload_bw()
>   drm/i915: Fix the MST PBN divider calculation
>
>  drivers/gpu/drm/drm_dp_mst_topology.c       | 24 +++++++++++++++------
>  drivers/gpu/drm/i915/display/intel_dp_mst.c |  4 +++-
>  include/drm/drm_dp_mst_helper.h             |  1 +
>  3 files changed, 22 insertions(+), 7 deletions(-)
>
Non-upstream changes to i915 for stable kernels is like volunteering to
test-drive the new SM studio...



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APPLIED [OEM-5.10] Re: [PATCH 1/2][F/G/U/OEM-5.10] UBUNTU: SAUCE: drm/dp/mst: Export drm_dp_get_vc_payload_bw()

Timo Aaltonen-6
In reply to this post by Koba Ko
On 27.1.2021 8.10, Koba Ko wrote:

> From: Imre Deak <[hidden email]>
>
> BugLink: https://bugs.launchpad.net/bugs/1913372
>
> This function will be needed by the next patch where the driver
> calculates the BW based on driver specific parameters, so export it.
>
> At the same time sanitize the function params, passing the more natural
> link rate instead of the encoding of the same rate.
>
> Cc: Lyude Paul <[hidden email]>
> Cc: Ville Syrjala <[hidden email]>
> Cc: <[hidden email]>
> Cc: [hidden email]
> Signed-off-by: Imre Deak <[hidden email]>
> Reviewed-by: Lyude Paul <[hidden email]>
> Reference: https://patchwork.freedesktop.org/series/86267/
> Signed-off-by: Koba Ko <[hidden email]>
> ---
>   drivers/gpu/drm/drm_dp_mst_topology.c | 24 ++++++++++++++++++------
>   include/drm/drm_dp_mst_helper.h       |  1 +
>   2 files changed, 19 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c
> index e87542533640..ae6bc2093479 100644
> --- a/drivers/gpu/drm/drm_dp_mst_topology.c
> +++ b/drivers/gpu/drm/drm_dp_mst_topology.c
> @@ -3629,14 +3629,26 @@ static int drm_dp_send_up_ack_reply(struct drm_dp_mst_topology_mgr *mgr,
>   return 0;
>   }
>  
> -static int drm_dp_get_vc_payload_bw(u8 dp_link_bw, u8  dp_link_count)
> +/**
> + * drm_dp_get_vc_payload_bw - get the VC payload BW for an MST link
> + * @rate: link rate in 10kbits/s units
> + * @lane_count: lane count
> + *
> + * Calculate the toal bandwidth of a MultiStream Transport link. The returned
> + * value is in units of PBNs/(timeslots/1 MTP). This value can be used to
> + * convert the number of PBNs required for a given stream to the number of
> + * timeslots this stream requires in each MTP.
> + */
> +int drm_dp_get_vc_payload_bw(int link_rate, int link_lane_count)
>   {
> - if (dp_link_bw == 0 || dp_link_count == 0)
> - DRM_DEBUG_KMS("invalid link bandwidth in DPCD: %x (link count: %d)\n",
> -      dp_link_bw, dp_link_count);
> + if (link_rate == 0 || link_lane_count == 0)
> + DRM_DEBUG_KMS("invalid link rate/lane count: (%d / %d)\n",
> +      link_rate, link_lane_count);
>  
> - return dp_link_bw * dp_link_count / 2;
> + /* See DP v2.0 2.6.4.2, VCPayload_Bandwidth_for_OneTimeSlotPer_MTP_Allocation */
> + return link_rate * link_lane_count / 54000;
>   }
> +EXPORT_SYMBOL(drm_dp_get_vc_payload_bw);
>  
>   /**
>    * drm_dp_read_mst_cap() - check whether or not a sink supports MST
> @@ -3692,7 +3704,7 @@ int drm_dp_mst_topology_mgr_set_mst(struct drm_dp_mst_topology_mgr *mgr, bool ms
>   goto out_unlock;
>   }
>  
> - mgr->pbn_div = drm_dp_get_vc_payload_bw(mgr->dpcd[1],
> + mgr->pbn_div = drm_dp_get_vc_payload_bw(drm_dp_bw_code_to_link_rate(mgr->dpcd[1]),
>   mgr->dpcd[2] & DP_MAX_LANE_COUNT_MASK);
>   if (mgr->pbn_div == 0) {
>   ret = -EINVAL;
> diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h
> index f5e92fe9151c..bd1c39907b92 100644
> --- a/include/drm/drm_dp_mst_helper.h
> +++ b/include/drm/drm_dp_mst_helper.h
> @@ -783,6 +783,7 @@ drm_dp_mst_detect_port(struct drm_connector *connector,
>  
>   struct edid *drm_dp_mst_get_edid(struct drm_connector *connector, struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port);
>  
> +int drm_dp_get_vc_payload_bw(int link_rate, int link_lane_count);
>  
>   int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc);
>  
>

applied to oem-5.10, thanks

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Re: [PATCH 0/2][F/G/U/OEM-5.10] UBUNTU: SAUCE: Fix the video can't output through WD19TB connected on TGL's Type-C port during cold-boot

Paolo Pisati-5
In reply to this post by Koba Ko
On Wed, Jan 27, 2021 at 02:10:01PM +0800, Koba Ko wrote:
> BugLink: https://bugs.launchpad.net/bugs/1913372

Recently posted, and no review yet upstream - i'll wait a bit before applying
it for H.
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NAK/cmt: Re: [PATCH 0/2][F/G/U/OEM-5.10] UBUNTU: SAUCE: Fix the video can't output through WD19TB connected on TGL's Type-C port during cold-boot

Paolo Pisati-5
In reply to this post by Koba Ko
On Wed, Jan 27, 2021 at 02:10:01PM +0800, Koba Ko wrote:
> BugLink: https://bugs.launchpad.net/bugs/1913372

Dropped your patches, instead cherry-picked the corresponding commits from
linux-next into H:

a321fc2b4e60 drm/dp/mst: Export drm_dp_get_vc_payload_bw()
b59c27cab257 drm/i915: Fix the MST PBN divider calculation
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Re: NAK/cmt: Re: [PATCH 0/2][F/G/U/OEM-5.10] UBUNTU: SAUCE: Fix the video can't output through WD19TB connected on TGL's Type-C port during cold-boot

Andrea Righi
On Fri, Feb 05, 2021 at 12:14:05PM +0100, Paolo Pisati wrote:
> On Wed, Jan 27, 2021 at 02:10:01PM +0800, Koba Ko wrote:
> > BugLink: https://bugs.launchpad.net/bugs/1913372
>
> Dropped your patches, instead cherry-picked the corresponding commits from
> linux-next into H:
>
> a321fc2b4e60 drm/dp/mst: Export drm_dp_get_vc_payload_bw()
> b59c27cab257 drm/i915: Fix the MST PBN divider calculation

I've done the same to unstable/5.11 (cherry-picked the same commits from
linux-next).

Thanks,
-Andrea

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Re: NAK/cmt: Re: [PATCH 0/2][F/G/U/OEM-5.10] UBUNTU: SAUCE: Fix the video can't output through WD19TB connected on TGL's Type-C port during cold-boot

Stefan Bader-2
In reply to this post by Paolo Pisati-5
On 05.02.21 12:14, Paolo Pisati wrote:
> On Wed, Jan 27, 2021 at 02:10:01PM +0800, Koba Ko wrote:
>> BugLink: https://bugs.launchpad.net/bugs/1913372
>
> Dropped your patches, instead cherry-picked the corresponding commits from
> linux-next into H:
>
> a321fc2b4e60 drm/dp/mst: Export drm_dp_get_vc_payload_bw()
> b59c27cab257 drm/i915: Fix the MST PBN divider calculation
>

Did you add the BugLink when cherry picking? Which IMO would be a better way of
doing this (it is the same patches, just now more upstream than before). So
instead of NAKing I'd say APPLIED/Cmnt here. Feels to better reflect the reality.

-Stefan


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ACK/Cmnt: [PATCH 0/2][F/G] Fix the video can't output through WD19TB connected on TGL's Type-C port during cold-boot

Stefan Bader-2
In reply to this post by Koba Ko
On 27.01.21 07:10, Koba Ko wrote:

> BugLink: https://bugs.launchpad.net/bugs/1913372
>
> [Impact]
> WD19TB would report the number of lane(2-lane) and it works well on Type-C port
> of TGL platform. Change the LTTPR mode to non-transparent mode, WD19TB would
> report the larger number of lane(4-lane). It's over the type-c port's bandwidth.
>
> [Fix]
> The patch is provided by Imre(https://patchwork.freedesktop.org/series/86267/).
> Calculate the PBN divider value based on the rate and lane count link parameters
> that the driver uses for all other computation.
>
> [Test Case]
> 1. Connected the WD19TB with the TGL platform's Type-C port and
> connected the external monitor on WD19TB with HDMI/Displayport.
> 2. Cold boot the TGL platform.
> 3. Check the monitor can be blinked and the video can output to the monitor.
>
> [Where problems could occur]
> It's correct to calculate the PBN divider based on the source's rate
> and lane count, not the mst's capability.
>
> Imre Deak (2):
>   drm/dp/mst: Export drm_dp_get_vc_payload_bw()
>   drm/i915: Fix the MST PBN divider calculation
>
>  drivers/gpu/drm/drm_dp_mst_topology.c       | 24 +++++++++++++++------
>  drivers/gpu/drm/i915/display/intel_dp_mst.c |  4 +++-
>  include/drm/drm_dp_mst_helper.h             |  1 +
>  3 files changed, 22 insertions(+), 7 deletions(-)
>
As Paolo reported those patches are now in linux-next. So when picking into G/F
we should prefer those (assumed identical) versions and just move BugLink and
s-o-b's ahead. At time of application we probably should even double-check
whether things have moved into the main kernel repo already.


a321fc2b4e60 drm/dp/mst: Export drm_dp_get_vc_payload_bw()
b59c27cab257 drm/i915: Fix the MST PBN divider calculation

Acked-by: Stefan Bader <[hidden email]>


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ACK: [PATCH 0/2][F/G/U/OEM-5.10] UBUNTU: SAUCE: Fix the video can't output through WD19TB connected on TGL's Type-C port during cold-boot

Kleber Souza
In reply to this post by Koba Ko
On 27.01.21 07:10, Koba Ko wrote:

> BugLink: https://bugs.launchpad.net/bugs/1913372
>
> [Impact]
> WD19TB would report the number of lane(2-lane) and it works well on Type-C port
> of TGL platform. Change the LTTPR mode to non-transparent mode, WD19TB would
> report the larger number of lane(4-lane). It's over the type-c port's bandwidth.
>
> [Fix]
> The patch is provided by Imre(https://patchwork.freedesktop.org/series/86267/).
> Calculate the PBN divider value based on the rate and lane count link parameters
> that the driver uses for all other computation.
>
> [Test Case]
> 1. Connected the WD19TB with the TGL platform's Type-C port and
> connected the external monitor on WD19TB with HDMI/Displayport.
> 2. Cold boot the TGL platform.
> 3. Check the monitor can be blinked and the video can output to the monitor.
>
> [Where problems could occur]
> It's correct to calculate the PBN divider based on the source's rate
> and lane count, not the mst's capability.
>
> Imre Deak (2):
>    drm/dp/mst: Export drm_dp_get_vc_payload_bw()
>    drm/i915: Fix the MST PBN divider calculation
>
>   drivers/gpu/drm/drm_dp_mst_topology.c       | 24 +++++++++++++++------
>   drivers/gpu/drm/i915/display/intel_dp_mst.c |  4 +++-
>   include/drm/drm_dp_mst_helper.h             |  1 +
>   3 files changed, 22 insertions(+), 7 deletions(-)
>

With Stefan's comments addressed:

Acked-by: Kleber Sacilotto de Souza <[hidden email]>

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APPLIED[G]/NACK[F]: [PATCH 0/2][F/G/U/OEM-5.10] UBUNTU: SAUCE: Fix the video can't output through WD19TB connected on TGL's Type-C port during cold-boot

Stefan Bader-2
In reply to this post by Koba Ko
On 27.01.21 07:10, Koba Ko wrote:

> BugLink: https://bugs.launchpad.net/bugs/1913372
>
> [Impact]
> WD19TB would report the number of lane(2-lane) and it works well on Type-C port
> of TGL platform. Change the LTTPR mode to non-transparent mode, WD19TB would
> report the larger number of lane(4-lane). It's over the type-c port's bandwidth.
>
> [Fix]
> The patch is provided by Imre(https://patchwork.freedesktop.org/series/86267/).
> Calculate the PBN divider value based on the rate and lane count link parameters
> that the driver uses for all other computation.
>
> [Test Case]
> 1. Connected the WD19TB with the TGL platform's Type-C port and
> connected the external monitor on WD19TB with HDMI/Displayport.
> 2. Cold boot the TGL platform.
> 3. Check the monitor can be blinked and the video can output to the monitor.
>
> [Where problems could occur]
> It's correct to calculate the PBN divider based on the source's rate
> and lane count, not the mst's capability.
>
> Imre Deak (2):
>   drm/dp/mst: Export drm_dp_get_vc_payload_bw()
>   drm/i915: Fix the MST PBN divider calculation
>
>  drivers/gpu/drm/drm_dp_mst_topology.c       | 24 +++++++++++++++------
>  drivers/gpu/drm/i915/display/intel_dp_mst.c |  4 +++-
>  include/drm/drm_dp_mst_helper.h             |  1 +
>  3 files changed, 22 insertions(+), 7 deletions(-)
>
Applied to groovy:linux/master-next. Both patches are now upstream and I picked
those instead of the provided SAUCE patches. However patch #1 does not apply at
all to focal. If you still think it should go into Focal/5.4, please re-submit
the upstream patches backported to Focal.

-Stefan


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