[PATCH 0/2][SRU][B][C] ELAN900C:00 04F3:2844 touchscreen doesn't work

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[PATCH 0/2][SRU][B][C] ELAN900C:00 04F3:2844 touchscreen doesn't work

AceLan Kao
BugLink: https://bugs.launchpad.net/bugs/1811335

[Impact]
[ELAN900C:00 04F3:2844] doesn't work

[Fix]
It works under kernel v4.19, so after bisect the kernel and got the first bad commit
   e50d95e2ad12 pinctrl: cannonlake: Fix HOSTSW_OWN register offset of H variant

[Test]
Verified on the DELL machine, the touchscreen works well.

[Regression Potential]
Low, the 2 commits are all
   Fixes: a663ccf0fea1 ("pinctrl: intel: Add Intel Cannon Lake PCH-H pin controller support")
Should be safe to be included.

Andy Shevchenko (1):
  pinctrl: cannonlake: Fix community ordering for H variant

Mika Westerberg (1):
  pinctrl: cannonlake: Fix HOSTSW_OWN register offset of H variant

 drivers/pinctrl/intel/pinctrl-cannonlake.c | 37 ++++++++++++----------
 1 file changed, 20 insertions(+), 17 deletions(-)

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2.17.1


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[PATCH 1/2][SRU][B][C] pinctrl: cannonlake: Fix community ordering for H variant

AceLan Kao
From: Andy Shevchenko <[hidden email]>

BugLink: https://bugs.launchpad.net/bugs/1811335

The driver was written based on an assumption that BIOS provides
unordered communities in ACPI DSDT. Nevertheless, it seems that
BIOS getting fixed before being provisioned to OxM:s.
So does driver.

BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=199911
Reported-by: Marc Landolt <[hidden email]>
Signed-off-by: Andy Shevchenko <[hidden email]>
Fixes: a663ccf0fea1 ("pinctrl: intel: Add Intel Cannon Lake PCH-H pin controller support")
Acked-by: Mika Westerberg <[hidden email]>
Signed-off-by: Linus Walleij <[hidden email]>
(cherry picked from commit 17ac526824a8b5544bc2545c76f489e49c6593a2)
Signed-off-by: AceLan Kao <[hidden email]>
---
 drivers/pinctrl/intel/pinctrl-cannonlake.c | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/drivers/pinctrl/intel/pinctrl-cannonlake.c b/drivers/pinctrl/intel/pinctrl-cannonlake.c
index 6243e7d95e7e..b294de0b661a 100644
--- a/drivers/pinctrl/intel/pinctrl-cannonlake.c
+++ b/drivers/pinctrl/intel/pinctrl-cannonlake.c
@@ -447,12 +447,8 @@ static const struct intel_function cnlh_functions[] = {
 static const struct intel_community cnlh_communities[] = {
  CNL_COMMUNITY(0, 0, 50, cnlh_community0_gpps),
  CNL_COMMUNITY(1, 51, 154, cnlh_community1_gpps),
- /*
- * ACPI MMIO resources are returned in reverse order for
- * communities 3 and 4.
- */
- CNL_COMMUNITY(3, 155, 248, cnlh_community3_gpps),
- CNL_COMMUNITY(2, 249, 298, cnlh_community4_gpps),
+ CNL_COMMUNITY(2, 155, 248, cnlh_community3_gpps),
+ CNL_COMMUNITY(3, 249, 298, cnlh_community4_gpps),
 };
 
 static const struct intel_pinctrl_soc_data cnlh_soc_data = {
--
2.17.1


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[PATCH 2/2][SRU][B][C] pinctrl: cannonlake: Fix HOSTSW_OWN register offset of H variant

AceLan Kao
In reply to this post by AceLan Kao
From: Mika Westerberg <[hidden email]>

BugLink: https://bugs.launchpad.net/bugs/1811335

It turns out the HOSTSW_OWN register offset is different between LP and
H variants. The latter should use 0xc0 instead so fix that.

Link: https://bugzilla.kernel.org/show_bug.cgi?id=199911
Fixes: a663ccf0fea1 ("pinctrl: intel: Add Intel Cannon Lake PCH-H pin controller support")
Signed-off-by: Mika Westerberg <[hidden email]>
Reviewed-by: Andy Shevchenko <[hidden email]>
Signed-off-by: Linus Walleij <[hidden email]>
(cherry picked from commit e50d95e2ad1266f8d3fcdf0724f03dbdffd400aa)
Signed-off-by: AceLan Kao <[hidden email]>
---
 drivers/pinctrl/intel/pinctrl-cannonlake.c | 33 +++++++++++++---------
 1 file changed, 20 insertions(+), 13 deletions(-)

diff --git a/drivers/pinctrl/intel/pinctrl-cannonlake.c b/drivers/pinctrl/intel/pinctrl-cannonlake.c
index b294de0b661a..965069d5a86d 100644
--- a/drivers/pinctrl/intel/pinctrl-cannonlake.c
+++ b/drivers/pinctrl/intel/pinctrl-cannonlake.c
@@ -18,10 +18,11 @@
 
 #include "pinctrl-intel.h"
 
-#define CNL_PAD_OWN 0x020
-#define CNL_PADCFGLOCK 0x080
-#define CNL_HOSTSW_OWN 0x0b0
-#define CNL_GPI_IE 0x120
+#define CNL_PAD_OWN 0x020
+#define CNL_PADCFGLOCK 0x080
+#define CNL_LP_HOSTSW_OWN 0x0b0
+#define CNL_H_HOSTSW_OWN 0x0c0
+#define CNL_GPI_IE 0x120
 
 #define CNL_GPP(r, s, e, g) \
  { \
@@ -33,12 +34,12 @@
 
 #define CNL_NO_GPIO -1
 
-#define CNL_COMMUNITY(b, s, e, g) \
+#define CNL_COMMUNITY(b, s, e, o, g) \
  { \
  .barno = (b), \
  .padown_offset = CNL_PAD_OWN, \
  .padcfglock_offset = CNL_PADCFGLOCK, \
- .hostown_offset = CNL_HOSTSW_OWN, \
+ .hostown_offset = (o), \
  .ie_offset = CNL_GPI_IE, \
  .pin_base = (s), \
  .npins = ((e) - (s) + 1), \
@@ -46,6 +47,12 @@
  .ngpps = ARRAY_SIZE(g), \
  }
 
+#define CNLLP_COMMUNITY(b, s, e, g) \
+ CNL_COMMUNITY(b, s, e, CNL_LP_HOSTSW_OWN, g)
+
+#define CNLH_COMMUNITY(b, s, e, g) \
+ CNL_COMMUNITY(b, s, e, CNL_H_HOSTSW_OWN, g)
+
 /* Cannon Lake-H */
 static const struct pinctrl_pin_desc cnlh_pins[] = {
  /* GPP_A */
@@ -445,10 +452,10 @@ static const struct intel_function cnlh_functions[] = {
 };
 
 static const struct intel_community cnlh_communities[] = {
- CNL_COMMUNITY(0, 0, 50, cnlh_community0_gpps),
- CNL_COMMUNITY(1, 51, 154, cnlh_community1_gpps),
- CNL_COMMUNITY(2, 155, 248, cnlh_community3_gpps),
- CNL_COMMUNITY(3, 249, 298, cnlh_community4_gpps),
+ CNLH_COMMUNITY(0, 0, 50, cnlh_community0_gpps),
+ CNLH_COMMUNITY(1, 51, 154, cnlh_community1_gpps),
+ CNLH_COMMUNITY(2, 155, 248, cnlh_community3_gpps),
+ CNLH_COMMUNITY(3, 249, 298, cnlh_community4_gpps),
 };
 
 static const struct intel_pinctrl_soc_data cnlh_soc_data = {
@@ -806,9 +813,9 @@ static const struct intel_padgroup cnllp_community4_gpps[] = {
 };
 
 static const struct intel_community cnllp_communities[] = {
- CNL_COMMUNITY(0, 0, 67, cnllp_community0_gpps),
- CNL_COMMUNITY(1, 68, 180, cnllp_community1_gpps),
- CNL_COMMUNITY(2, 181, 243, cnllp_community4_gpps),
+ CNLLP_COMMUNITY(0, 0, 67, cnllp_community0_gpps),
+ CNLLP_COMMUNITY(1, 68, 180, cnllp_community1_gpps),
+ CNLLP_COMMUNITY(2, 181, 243, cnllp_community4_gpps),
 };
 
 static const struct intel_pinctrl_soc_data cnllp_soc_data = {
--
2.17.1


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ACK: [PATCH 0/2][SRU][B][C] ELAN900C:00 04F3:2844 touchscreen doesn't work

Stefan Bader-2
In reply to this post by AceLan Kao
On 11.01.19 08:46, AceLan Kao wrote:

> BugLink: https://bugs.launchpad.net/bugs/1811335
>
> [Impact]
> [ELAN900C:00 04F3:2844] doesn't work
>
> [Fix]
> It works under kernel v4.19, so after bisect the kernel and got the first bad commit
>    e50d95e2ad12 pinctrl: cannonlake: Fix HOSTSW_OWN register offset of H variant
>
> [Test]
> Verified on the DELL machine, the touchscreen works well.
>
> [Regression Potential]
> Low, the 2 commits are all
>    Fixes: a663ccf0fea1 ("pinctrl: intel: Add Intel Cannon Lake PCH-H pin controller support")
> Should be safe to be included.
>
> Andy Shevchenko (1):
>   pinctrl: cannonlake: Fix community ordering for H variant
>
> Mika Westerberg (1):
>   pinctrl: cannonlake: Fix HOSTSW_OWN register offset of H variant
>
>  drivers/pinctrl/intel/pinctrl-cannonlake.c | 37 ++++++++++++----------
>  1 file changed, 20 insertions(+), 17 deletions(-)
>
Acked-by: Stefan Bader <[hidden email]>


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ACK: [PATCH 0/2][SRU][B][C] ELAN900C:00 04F3:2844 touchscreen doesn't work

Colin Ian King-2
In reply to this post by AceLan Kao
On 11/01/2019 07:46, AceLan Kao wrote:

> BugLink: https://bugs.launchpad.net/bugs/1811335
>
> [Impact]
> [ELAN900C:00 04F3:2844] doesn't work
>
> [Fix]
> It works under kernel v4.19, so after bisect the kernel and got the first bad commit
>    e50d95e2ad12 pinctrl: cannonlake: Fix HOSTSW_OWN register offset of H variant
>
> [Test]
> Verified on the DELL machine, the touchscreen works well.
>
> [Regression Potential]
> Low, the 2 commits are all
>    Fixes: a663ccf0fea1 ("pinctrl: intel: Add Intel Cannon Lake PCH-H pin controller support")
> Should be safe to be included.
>
> Andy Shevchenko (1):
>   pinctrl: cannonlake: Fix community ordering for H variant
>
> Mika Westerberg (1):
>   pinctrl: cannonlake: Fix HOSTSW_OWN register offset of H variant
>
>  drivers/pinctrl/intel/pinctrl-cannonlake.c | 37 ++++++++++++----------
>  1 file changed, 20 insertions(+), 17 deletions(-)
>

Clean cherry picks, fixes known issue. Thanks.

Acked-by: Colin Ian King <[hidden email]>

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APPLIED: [PATCH 0/2][SRU][B][C] ELAN900C:00 04F3:2844 touchscreen doesn't work

Kleber Souza
In reply to this post by AceLan Kao
On 1/11/19 8:46 AM, AceLan Kao wrote:

> BugLink: https://bugs.launchpad.net/bugs/1811335
>
> [Impact]
> [ELAN900C:00 04F3:2844] doesn't work
>
> [Fix]
> It works under kernel v4.19, so after bisect the kernel and got the first bad commit
>    e50d95e2ad12 pinctrl: cannonlake: Fix HOSTSW_OWN register offset of H variant
>
> [Test]
> Verified on the DELL machine, the touchscreen works well.
>
> [Regression Potential]
> Low, the 2 commits are all
>    Fixes: a663ccf0fea1 ("pinctrl: intel: Add Intel Cannon Lake PCH-H pin controller support")
> Should be safe to be included.
>
> Andy Shevchenko (1):
>   pinctrl: cannonlake: Fix community ordering for H variant
>
> Mika Westerberg (1):
>   pinctrl: cannonlake: Fix HOSTSW_OWN register offset of H variant
>
>  drivers/pinctrl/intel/pinctrl-cannonlake.c | 37 ++++++++++++----------
>  1 file changed, 20 insertions(+), 17 deletions(-)
>
Applied to bionic/master-next and cosmic/master-next branches.

Thanks,
Kleber


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