[PATCH 0/3][SRU Artful] Workaround Falkor erratum 1041

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[PATCH 0/3][SRU Artful] Workaround Falkor erratum 1041

dann frazier-4
BugLink: https://bugs.launchpad.net/1738497

All clean cherry-picks from upstream, other than a trivial Kconfig offset
adjustment.

Shanker Donthineni (2):
  arm64: Define cputype macros for Falkor CPU
  arm64: Add software workaround for Falkor erratum 1041

dann frazier (1):
  UBUNTU: [Config] CONFIG_QCOM_FALKOR_ERRATUM_E1041=y

 Documentation/arm64/silicon-errata.txt    |  1 +
 arch/arm64/Kconfig                        | 10 ++++++++++
 arch/arm64/include/asm/assembler.h        | 10 ++++++++++
 arch/arm64/include/asm/cputype.h          |  2 ++
 arch/arm64/kernel/cpu-reset.S             |  1 +
 arch/arm64/kernel/efi-entry.S             |  2 ++
 arch/arm64/kernel/head.S                  |  1 +
 arch/arm64/kernel/relocate_kernel.S       |  1 +
 arch/arm64/kvm/hyp-init.S                 |  1 +
 debian.master/config/annotations          |  2 ++
 debian.master/config/config.common.ubuntu |  1 +
 11 files changed, 32 insertions(+)

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[PATCH 1/3][SRU Artful] arm64: Define cputype macros for Falkor CPU

dann frazier-4
From: Shanker Donthineni <[hidden email]>

BugLink: https://bugs.launchpad.net/bugs/1738497

Add cputype definition macros for Qualcomm Datacenter Technologies
Falkor CPU in cputype.h. It's unfortunate that the first revision
of the Falkor CPU used the wrong part number 0x800, got fixed in v2
chip with part number 0xC00, and would be used the same value for
future revisions.

Signed-off-by: Shanker Donthineni <[hidden email]>
Signed-off-by: Will Deacon <[hidden email]>
(cherry picked from commit c622cc013cece073722592cff1ac6643a33b1622)
Signed-off-by: dann frazier <[hidden email]>
---
 arch/arm64/include/asm/cputype.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index 235e77d98261..cbf08d7cbf30 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -91,6 +91,7 @@
 #define BRCM_CPU_PART_VULCAN 0x516
 
 #define QCOM_CPU_PART_FALKOR_V1 0x800
+#define QCOM_CPU_PART_FALKOR 0xC00
 
 #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
 #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
@@ -99,6 +100,7 @@
 #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
 #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)
 #define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1)
+#define MIDR_QCOM_FALKOR MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR)
 
 #ifndef __ASSEMBLY__
 
--
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[PATCH 2/3][SRU Artful] UBUNTU: [Config] CONFIG_QCOM_FALKOR_ERRATUM_E1041=y

dann frazier-4
In reply to this post by dann frazier-4
BugLink: https://bugs.launchpad.net/bugs/1738947

Signed-off-by: dann frazier <[hidden email]>
---
 debian.master/config/annotations          | 2 ++
 debian.master/config/config.common.ubuntu | 1 +
 2 files changed, 3 insertions(+)

diff --git a/debian.master/config/annotations b/debian.master/config/annotations
index b4656baf9d28..2d2e2a139ebb 100644
--- a/debian.master/config/annotations
+++ b/debian.master/config/annotations
@@ -11632,10 +11632,12 @@ CONFIG_APPLDATA_NET_SUM                         policy<{'s390x': 'm'}>
 
 CONFIG_ARM64_ERRATUM_843419                     policy<{'arm64': 'y'}>
 CONFIG_ARM64_ERRATUM_858921                     policy<{'arm64': 'y'}>
+CONFIG_QCOM_FALKOR_ERRATUM_E1041                policy<{'arm64': 'y'}>
 CONFIG_QCOM_QDF2400_ERRATUM_0065                policy<{'arm64': 'y'}>
 #
 CONFIG_ARM64_ERRATUM_843419                     cmark<ENFORCED> note<LP#1647793>
 CONFIG_ARM64_ERRATUM_858921                     cmark<ENFORCED> note<LP#1675509>
+CONFIG_QCOM_FALKOR_ERRATUM_E1041                mark<ENFORCED> note<LP#1738947>
 CONFIG_QCOM_QDF2400_ERRATUM_0065                mark<ENFORCED> note<LP#1672486>
 #
 CONFIG_HVC_UDBG                                 mark<ENFORCED> note<LP#1680888>
diff --git a/debian.master/config/config.common.ubuntu b/debian.master/config/config.common.ubuntu
index 243a2e2fbb60..8f9a3b9e01f3 100644
--- a/debian.master/config/config.common.ubuntu
+++ b/debian.master/config/config.common.ubuntu
@@ -6840,6 +6840,7 @@ CONFIG_QCOM_EBI2=y
 CONFIG_QCOM_EMAC=m
 CONFIG_QCOM_FALKOR_ERRATUM_1003=y
 CONFIG_QCOM_FALKOR_ERRATUM_1009=y
+CONFIG_QCOM_FALKOR_ERRATUM_E1041=y
 CONFIG_QCOM_GDSC=y
 CONFIG_QCOM_GSBI=m
 CONFIG_QCOM_HIDMA=m
--
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[PATCH 3/3][SRU Artful] arm64: Add software workaround for Falkor erratum 1041

dann frazier-4
In reply to this post by dann frazier-4
From: Shanker Donthineni <[hidden email]>

BugLink: https://bugs.launchpad.net/bugs/1738497

The ARM architecture defines the memory locations that are permitted
to be accessed as the result of a speculative instruction fetch from
an exception level for which all stages of translation are disabled.
Specifically, the core is permitted to speculatively fetch from the
4KB region containing the current program counter 4K and next 4K.

When translation is changed from enabled to disabled for the running
exception level (SCTLR_ELn[M] changed from a value of 1 to 0), the
Falkor core may errantly speculatively access memory locations outside
of the 4KB region permitted by the architecture. The errant memory
access may lead to one of the following unexpected behaviors.

1) A System Error Interrupt (SEI) being raised by the Falkor core due
   to the errant memory access attempting to access a region of memory
   that is protected by a slave-side memory protection unit.
2) Unpredictable device behavior due to a speculative read from device
   memory. This behavior may only occur if the instruction cache is
   disabled prior to or coincident with translation being changed from
   enabled to disabled.

The conditions leading to this erratum will not occur when either of the
following occur:
 1) A higher exception level disables translation of a lower exception level
   (e.g. EL2 changing SCTLR_EL1[M] from a value of 1 to 0).
 2) An exception level disabling its stage-1 translation if its stage-2
    translation is enabled (e.g. EL1 changing SCTLR_EL1[M] from a value of 1
    to 0 when HCR_EL2[VM] has a value of 1).

To avoid the errant behavior, software must execute an ISB immediately
prior to executing the MSR that will change SCTLR_ELn[M] from 1 to 0.

Signed-off-by: Shanker Donthineni <[hidden email]>
Signed-off-by: Will Deacon <[hidden email]>
(backported from commit 932b50c7c1c65e6f23002e075b97ee083c4a9e71)
[ dannf: trivial offset fix in Kconfig ]
Signed-off-by: dann frazier <[hidden email]>
---
 Documentation/arm64/silicon-errata.txt |  1 +
 arch/arm64/Kconfig                     | 10 ++++++++++
 arch/arm64/include/asm/assembler.h     | 10 ++++++++++
 arch/arm64/kernel/cpu-reset.S          |  1 +
 arch/arm64/kernel/efi-entry.S          |  2 ++
 arch/arm64/kernel/head.S               |  1 +
 arch/arm64/kernel/relocate_kernel.S    |  1 +
 arch/arm64/kvm/hyp-init.S              |  1 +
 8 files changed, 27 insertions(+)

diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt
index 66e8ce14d23d..704770c0edf2 100644
--- a/Documentation/arm64/silicon-errata.txt
+++ b/Documentation/arm64/silicon-errata.txt
@@ -74,3 +74,4 @@ stable kernels.
 | Qualcomm Tech. | Falkor v1       | E1003           | QCOM_FALKOR_ERRATUM_1003    |
 | Qualcomm Tech. | Falkor v1       | E1009           | QCOM_FALKOR_ERRATUM_1009    |
 | Qualcomm Tech. | QDF2400 ITS     | E0065           | QCOM_QDF2400_ERRATUM_0065   |
+| Qualcomm Tech. | Falkor v{1,2}   | E1041           | QCOM_FALKOR_ERRATUM_1041    |
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 98dcaf82fbe6..082136662e8b 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -538,6 +538,16 @@ config QCOM_QDF2400_ERRATUM_0065
 
   If unsure, say Y.
 
+config QCOM_FALKOR_ERRATUM_E1041
+ bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
+ default y
+ help
+  Falkor CPU may speculatively fetch instructions from an improper
+  memory location when MMU translation is changed from SCTLR_ELn[M]=1
+  to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
+
+  If unsure, say Y.
+
 endmenu
 
 
diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h
index 1b67c3782d00..1f049ef92301 100644
--- a/arch/arm64/include/asm/assembler.h
+++ b/arch/arm64/include/asm/assembler.h
@@ -476,4 +476,14 @@ alternative_else_nop_endif
 #endif
  .endm
 
+/**
+ * Errata workaround prior to disable MMU. Insert an ISB immediately prior
+ * to executing the MSR that will change SCTLR_ELn[M] from a value of 1 to 0.
+ */
+ .macro pre_disable_mmu_workaround
+#ifdef CONFIG_QCOM_FALKOR_ERRATUM_E1041
+ isb
+#endif
+ .endm
+
 #endif /* __ASM_ASSEMBLER_H */
diff --git a/arch/arm64/kernel/cpu-reset.S b/arch/arm64/kernel/cpu-reset.S
index 65f42d257414..2a752cb2a0f3 100644
--- a/arch/arm64/kernel/cpu-reset.S
+++ b/arch/arm64/kernel/cpu-reset.S
@@ -37,6 +37,7 @@ ENTRY(__cpu_soft_restart)
  mrs x12, sctlr_el1
  ldr x13, =SCTLR_ELx_FLAGS
  bic x12, x12, x13
+ pre_disable_mmu_workaround
  msr sctlr_el1, x12
  isb
 
diff --git a/arch/arm64/kernel/efi-entry.S b/arch/arm64/kernel/efi-entry.S
index 4e6ad355bd05..6b9736c3fb56 100644
--- a/arch/arm64/kernel/efi-entry.S
+++ b/arch/arm64/kernel/efi-entry.S
@@ -96,6 +96,7 @@ ENTRY(entry)
  mrs x0, sctlr_el2
  bic x0, x0, #1 << 0 // clear SCTLR.M
  bic x0, x0, #1 << 2 // clear SCTLR.C
+ pre_disable_mmu_workaround
  msr sctlr_el2, x0
  isb
  b 2f
@@ -103,6 +104,7 @@ ENTRY(entry)
  mrs x0, sctlr_el1
  bic x0, x0, #1 << 0 // clear SCTLR.M
  bic x0, x0, #1 << 2 // clear SCTLR.C
+ pre_disable_mmu_workaround
  msr sctlr_el1, x0
  isb
 2:
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index 8c908829d3c4..63515734ebdf 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@ -728,6 +728,7 @@ __primary_switch:
  * to take into account by discarding the current kernel mapping and
  * creating a new one.
  */
+ pre_disable_mmu_workaround
  msr sctlr_el1, x20 // disable the MMU
  isb
  bl __create_page_tables // recreate kernel mapping
diff --git a/arch/arm64/kernel/relocate_kernel.S b/arch/arm64/kernel/relocate_kernel.S
index ce704a4aeadd..f407e422a720 100644
--- a/arch/arm64/kernel/relocate_kernel.S
+++ b/arch/arm64/kernel/relocate_kernel.S
@@ -45,6 +45,7 @@ ENTRY(arm64_relocate_new_kernel)
  mrs x0, sctlr_el2
  ldr x1, =SCTLR_ELx_FLAGS
  bic x0, x0, x1
+ pre_disable_mmu_workaround
  msr sctlr_el2, x0
  isb
 1:
diff --git a/arch/arm64/kvm/hyp-init.S b/arch/arm64/kvm/hyp-init.S
index 3f9615582377..870828c364c5 100644
--- a/arch/arm64/kvm/hyp-init.S
+++ b/arch/arm64/kvm/hyp-init.S
@@ -151,6 +151,7 @@ reset:
  mrs x5, sctlr_el2
  ldr x6, =SCTLR_ELx_FLAGS
  bic x5, x5, x6 // Clear SCTL_M and etc
+ pre_disable_mmu_workaround
  msr sctlr_el2, x5
  isb
 
--
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[RESEND][PATCH 1/3][SRU Artful] arm64: Define cputype macros for Falkor CPU

dann frazier-4
In reply to this post by dann frazier-4
From: Shanker Donthineni <[hidden email]>

BugLink: https://bugs.launchpad.net/bugs/1738497

Add cputype definition macros for Qualcomm Datacenter Technologies
Falkor CPU in cputype.h. It's unfortunate that the first revision
of the Falkor CPU used the wrong part number 0x800, got fixed in v2
chip with part number 0xC00, and would be used the same value for
future revisions.

Signed-off-by: Shanker Donthineni <[hidden email]>
Signed-off-by: Will Deacon <[hidden email]>
(cherry picked from commit c622cc013cece073722592cff1ac6643a33b1622)
Signed-off-by: dann frazier <[hidden email]>
---
 arch/arm64/include/asm/cputype.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index 235e77d98261..cbf08d7cbf30 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -91,6 +91,7 @@
 #define BRCM_CPU_PART_VULCAN 0x516
 
 #define QCOM_CPU_PART_FALKOR_V1 0x800
+#define QCOM_CPU_PART_FALKOR 0xC00
 
 #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
 #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
@@ -99,6 +100,7 @@
 #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
 #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)
 #define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1)
+#define MIDR_QCOM_FALKOR MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR)
 
 #ifndef __ASSEMBLY__
 
--
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[RESEND][PATCH 2/3][SRU Artful] UBUNTU: [Config] CONFIG_QCOM_FALKOR_ERRATUM_E1041=y

dann frazier-4
In reply to this post by dann frazier-4
BugLink: https://bugs.launchpad.net/bugs/1738947

Signed-off-by: dann frazier <[hidden email]>
---
 debian.master/config/annotations          | 2 ++
 debian.master/config/config.common.ubuntu | 1 +
 2 files changed, 3 insertions(+)

diff --git a/debian.master/config/annotations b/debian.master/config/annotations
index b4656baf9d28..2d2e2a139ebb 100644
--- a/debian.master/config/annotations
+++ b/debian.master/config/annotations
@@ -11632,10 +11632,12 @@ CONFIG_APPLDATA_NET_SUM                         policy<{'s390x': 'm'}>
 
 CONFIG_ARM64_ERRATUM_843419                     policy<{'arm64': 'y'}>
 CONFIG_ARM64_ERRATUM_858921                     policy<{'arm64': 'y'}>
+CONFIG_QCOM_FALKOR_ERRATUM_E1041                policy<{'arm64': 'y'}>
 CONFIG_QCOM_QDF2400_ERRATUM_0065                policy<{'arm64': 'y'}>
 #
 CONFIG_ARM64_ERRATUM_843419                     cmark<ENFORCED> note<LP#1647793>
 CONFIG_ARM64_ERRATUM_858921                     cmark<ENFORCED> note<LP#1675509>
+CONFIG_QCOM_FALKOR_ERRATUM_E1041                mark<ENFORCED> note<LP#1738947>
 CONFIG_QCOM_QDF2400_ERRATUM_0065                mark<ENFORCED> note<LP#1672486>
 #
 CONFIG_HVC_UDBG                                 mark<ENFORCED> note<LP#1680888>
diff --git a/debian.master/config/config.common.ubuntu b/debian.master/config/config.common.ubuntu
index 243a2e2fbb60..8f9a3b9e01f3 100644
--- a/debian.master/config/config.common.ubuntu
+++ b/debian.master/config/config.common.ubuntu
@@ -6840,6 +6840,7 @@ CONFIG_QCOM_EBI2=y
 CONFIG_QCOM_EMAC=m
 CONFIG_QCOM_FALKOR_ERRATUM_1003=y
 CONFIG_QCOM_FALKOR_ERRATUM_1009=y
+CONFIG_QCOM_FALKOR_ERRATUM_E1041=y
 CONFIG_QCOM_GDSC=y
 CONFIG_QCOM_GSBI=m
 CONFIG_QCOM_HIDMA=m
--
2.15.1


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[RESEND][PATCH 3/3][SRU Artful] arm64: Add software workaround for Falkor erratum 1041

dann frazier-4
In reply to this post by dann frazier-4
From: Shanker Donthineni <[hidden email]>

BugLink: https://bugs.launchpad.net/bugs/1738497

The ARM architecture defines the memory locations that are permitted
to be accessed as the result of a speculative instruction fetch from
an exception level for which all stages of translation are disabled.
Specifically, the core is permitted to speculatively fetch from the
4KB region containing the current program counter 4K and next 4K.

When translation is changed from enabled to disabled for the running
exception level (SCTLR_ELn[M] changed from a value of 1 to 0), the
Falkor core may errantly speculatively access memory locations outside
of the 4KB region permitted by the architecture. The errant memory
access may lead to one of the following unexpected behaviors.

1) A System Error Interrupt (SEI) being raised by the Falkor core due
   to the errant memory access attempting to access a region of memory
   that is protected by a slave-side memory protection unit.
2) Unpredictable device behavior due to a speculative read from device
   memory. This behavior may only occur if the instruction cache is
   disabled prior to or coincident with translation being changed from
   enabled to disabled.

The conditions leading to this erratum will not occur when either of the
following occur:
 1) A higher exception level disables translation of a lower exception level
   (e.g. EL2 changing SCTLR_EL1[M] from a value of 1 to 0).
 2) An exception level disabling its stage-1 translation if its stage-2
    translation is enabled (e.g. EL1 changing SCTLR_EL1[M] from a value of 1
    to 0 when HCR_EL2[VM] has a value of 1).

To avoid the errant behavior, software must execute an ISB immediately
prior to executing the MSR that will change SCTLR_ELn[M] from 1 to 0.

Signed-off-by: Shanker Donthineni <[hidden email]>
Signed-off-by: Will Deacon <[hidden email]>
(backported from commit 932b50c7c1c65e6f23002e075b97ee083c4a9e71)
[ dannf: trivial offset fix in Kconfig ]
Signed-off-by: dann frazier <[hidden email]>
---
 Documentation/arm64/silicon-errata.txt |  1 +
 arch/arm64/Kconfig                     | 10 ++++++++++
 arch/arm64/include/asm/assembler.h     | 10 ++++++++++
 arch/arm64/kernel/cpu-reset.S          |  1 +
 arch/arm64/kernel/efi-entry.S          |  2 ++
 arch/arm64/kernel/head.S               |  1 +
 arch/arm64/kernel/relocate_kernel.S    |  1 +
 arch/arm64/kvm/hyp-init.S              |  1 +
 8 files changed, 27 insertions(+)

diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt
index 66e8ce14d23d..704770c0edf2 100644
--- a/Documentation/arm64/silicon-errata.txt
+++ b/Documentation/arm64/silicon-errata.txt
@@ -74,3 +74,4 @@ stable kernels.
 | Qualcomm Tech. | Falkor v1       | E1003           | QCOM_FALKOR_ERRATUM_1003    |
 | Qualcomm Tech. | Falkor v1       | E1009           | QCOM_FALKOR_ERRATUM_1009    |
 | Qualcomm Tech. | QDF2400 ITS     | E0065           | QCOM_QDF2400_ERRATUM_0065   |
+| Qualcomm Tech. | Falkor v{1,2}   | E1041           | QCOM_FALKOR_ERRATUM_1041    |
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 98dcaf82fbe6..082136662e8b 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -538,6 +538,16 @@ config QCOM_QDF2400_ERRATUM_0065
 
   If unsure, say Y.
 
+config QCOM_FALKOR_ERRATUM_E1041
+ bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
+ default y
+ help
+  Falkor CPU may speculatively fetch instructions from an improper
+  memory location when MMU translation is changed from SCTLR_ELn[M]=1
+  to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
+
+  If unsure, say Y.
+
 endmenu
 
 
diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h
index 1b67c3782d00..1f049ef92301 100644
--- a/arch/arm64/include/asm/assembler.h
+++ b/arch/arm64/include/asm/assembler.h
@@ -476,4 +476,14 @@ alternative_else_nop_endif
 #endif
  .endm
 
+/**
+ * Errata workaround prior to disable MMU. Insert an ISB immediately prior
+ * to executing the MSR that will change SCTLR_ELn[M] from a value of 1 to 0.
+ */
+ .macro pre_disable_mmu_workaround
+#ifdef CONFIG_QCOM_FALKOR_ERRATUM_E1041
+ isb
+#endif
+ .endm
+
 #endif /* __ASM_ASSEMBLER_H */
diff --git a/arch/arm64/kernel/cpu-reset.S b/arch/arm64/kernel/cpu-reset.S
index 65f42d257414..2a752cb2a0f3 100644
--- a/arch/arm64/kernel/cpu-reset.S
+++ b/arch/arm64/kernel/cpu-reset.S
@@ -37,6 +37,7 @@ ENTRY(__cpu_soft_restart)
  mrs x12, sctlr_el1
  ldr x13, =SCTLR_ELx_FLAGS
  bic x12, x12, x13
+ pre_disable_mmu_workaround
  msr sctlr_el1, x12
  isb
 
diff --git a/arch/arm64/kernel/efi-entry.S b/arch/arm64/kernel/efi-entry.S
index 4e6ad355bd05..6b9736c3fb56 100644
--- a/arch/arm64/kernel/efi-entry.S
+++ b/arch/arm64/kernel/efi-entry.S
@@ -96,6 +96,7 @@ ENTRY(entry)
  mrs x0, sctlr_el2
  bic x0, x0, #1 << 0 // clear SCTLR.M
  bic x0, x0, #1 << 2 // clear SCTLR.C
+ pre_disable_mmu_workaround
  msr sctlr_el2, x0
  isb
  b 2f
@@ -103,6 +104,7 @@ ENTRY(entry)
  mrs x0, sctlr_el1
  bic x0, x0, #1 << 0 // clear SCTLR.M
  bic x0, x0, #1 << 2 // clear SCTLR.C
+ pre_disable_mmu_workaround
  msr sctlr_el1, x0
  isb
 2:
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index 8c908829d3c4..63515734ebdf 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@ -728,6 +728,7 @@ __primary_switch:
  * to take into account by discarding the current kernel mapping and
  * creating a new one.
  */
+ pre_disable_mmu_workaround
  msr sctlr_el1, x20 // disable the MMU
  isb
  bl __create_page_tables // recreate kernel mapping
diff --git a/arch/arm64/kernel/relocate_kernel.S b/arch/arm64/kernel/relocate_kernel.S
index ce704a4aeadd..f407e422a720 100644
--- a/arch/arm64/kernel/relocate_kernel.S
+++ b/arch/arm64/kernel/relocate_kernel.S
@@ -45,6 +45,7 @@ ENTRY(arm64_relocate_new_kernel)
  mrs x0, sctlr_el2
  ldr x1, =SCTLR_ELx_FLAGS
  bic x0, x0, x1
+ pre_disable_mmu_workaround
  msr sctlr_el2, x0
  isb
 1:
diff --git a/arch/arm64/kvm/hyp-init.S b/arch/arm64/kvm/hyp-init.S
index 3f9615582377..870828c364c5 100644
--- a/arch/arm64/kvm/hyp-init.S
+++ b/arch/arm64/kvm/hyp-init.S
@@ -151,6 +151,7 @@ reset:
  mrs x5, sctlr_el2
  ldr x6, =SCTLR_ELx_FLAGS
  bic x5, x5, x6 // Clear SCTL_M and etc
+ pre_disable_mmu_workaround
  msr sctlr_el2, x5
  isb
 
--
2.15.1


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ACK: [PATCH 0/3][SRU Artful] Workaround Falkor erratum 1041

Stefan Bader-2
In reply to this post by dann frazier-4
On 18.12.2017 19:53, dann frazier wrote:

> BugLink: https://bugs.launchpad.net/1738497
>
> All clean cherry-picks from upstream, other than a trivial Kconfig offset
> adjustment.
>
> Shanker Donthineni (2):
>   arm64: Define cputype macros for Falkor CPU
>   arm64: Add software workaround for Falkor erratum 1041
>
> dann frazier (1):
>   UBUNTU: [Config] CONFIG_QCOM_FALKOR_ERRATUM_E1041=y
>
>  Documentation/arm64/silicon-errata.txt    |  1 +
>  arch/arm64/Kconfig                        | 10 ++++++++++
>  arch/arm64/include/asm/assembler.h        | 10 ++++++++++
>  arch/arm64/include/asm/cputype.h          |  2 ++
>  arch/arm64/kernel/cpu-reset.S             |  1 +
>  arch/arm64/kernel/efi-entry.S             |  2 ++
>  arch/arm64/kernel/head.S                  |  1 +
>  arch/arm64/kernel/relocate_kernel.S       |  1 +
>  arch/arm64/kvm/hyp-init.S                 |  1 +
>  debian.master/config/annotations          |  2 ++
>  debian.master/config/config.common.ubuntu |  1 +
>  11 files changed, 32 insertions(+)
>
Acked-by: Stefan Bader <[hidden email]>



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ACK: [PATCH 0/3][SRU Artful] Workaround Falkor erratum 1041

Colin Ian King-2
In reply to this post by dann frazier-4
On 18/12/17 18:53, dann frazier wrote:

> BugLink: https://bugs.launchpad.net/1738497
>
> All clean cherry-picks from upstream, other than a trivial Kconfig offset
> adjustment.
>
> Shanker Donthineni (2):
>   arm64: Define cputype macros for Falkor CPU
>   arm64: Add software workaround for Falkor erratum 1041
>
> dann frazier (1):
>   UBUNTU: [Config] CONFIG_QCOM_FALKOR_ERRATUM_E1041=y
>
>  Documentation/arm64/silicon-errata.txt    |  1 +
>  arch/arm64/Kconfig                        | 10 ++++++++++
>  arch/arm64/include/asm/assembler.h        | 10 ++++++++++
>  arch/arm64/include/asm/cputype.h          |  2 ++
>  arch/arm64/kernel/cpu-reset.S             |  1 +
>  arch/arm64/kernel/efi-entry.S             |  2 ++
>  arch/arm64/kernel/head.S                  |  1 +
>  arch/arm64/kernel/relocate_kernel.S       |  1 +
>  arch/arm64/kvm/hyp-init.S                 |  1 +
>  debian.master/config/annotations          |  2 ++
>  debian.master/config/config.common.ubuntu |  1 +
>  11 files changed, 32 insertions(+)
>

Looks sane to me, changes limited to Falkor v{1,2} so minimal regression
potential.

Acked-by: Colin Ian King <[hidden email]>

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APPLIED: [PATCH 0/3][SRU Artful] Workaround Falkor erratum 1041

Khalid Elmously
In reply to this post by dann frazier-4
Applied to Artful

On 2017-12-18 11:53:32 , dann frazier wrote:

> BugLink: https://bugs.launchpad.net/1738497
>
> All clean cherry-picks from upstream, other than a trivial Kconfig offset
> adjustment.
>
> Shanker Donthineni (2):
>   arm64: Define cputype macros for Falkor CPU
>   arm64: Add software workaround for Falkor erratum 1041
>
> dann frazier (1):
>   UBUNTU: [Config] CONFIG_QCOM_FALKOR_ERRATUM_E1041=y
>
>  Documentation/arm64/silicon-errata.txt    |  1 +
>  arch/arm64/Kconfig                        | 10 ++++++++++
>  arch/arm64/include/asm/assembler.h        | 10 ++++++++++
>  arch/arm64/include/asm/cputype.h          |  2 ++
>  arch/arm64/kernel/cpu-reset.S             |  1 +
>  arch/arm64/kernel/efi-entry.S             |  2 ++
>  arch/arm64/kernel/head.S                  |  1 +
>  arch/arm64/kernel/relocate_kernel.S       |  1 +
>  arch/arm64/kvm/hyp-init.S                 |  1 +
>  debian.master/config/annotations          |  2 ++
>  debian.master/config/config.common.ubuntu |  1 +
>  11 files changed, 32 insertions(+)
>
> --
> 2.15.1
>
>
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