[PATCH 0/3] [SRU][Bionic] drm/i915: Fix softpin on 32bit

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[PATCH 0/3] [SRU][Bionic] drm/i915: Fix softpin on 32bit

Timo Aaltonen-6
BugLink: https://bugs.launchpad.net/bugs/1815172

We've been carrying a commit reverting softpin support from mesa in bionic,
because softpin support was broken on 4.15 and 4.18. The patches to fix it
were sent to stable@ but not all of them got applied to 4.15.x because there
were minor conflicts. The patch for drm/i915/gvt was added to make the other
one cherry-pick cleanly.

The reason to get these backported is so that we can drop the revert from
mesa, because it actually broke Ice Lake which apparently requires softpin
support in the DRI driver.

Chris Wilson (2):
  drm/i915: Mark up GTT sizes as u64
  drm/i915: Compare user's 64b GTT offset even on 32b

Zhi Wang (1):
  drm/i915/gvt: Use I915_GTT_PAGE_SIZE

 drivers/gpu/drm/i915/gvt/cmd_parser.c         | 13 ++---
 drivers/gpu/drm/i915/gvt/execlist.c           |  2 +-
 drivers/gpu/drm/i915/gvt/gtt.c                | 51 ++++++++++---------
 drivers/gpu/drm/i915/gvt/gtt.h                |  6 +--
 drivers/gpu/drm/i915/gvt/reg.h                |  3 +-
 drivers/gpu/drm/i915/gvt/scheduler.c          | 12 ++---
 drivers/gpu/drm/i915/i915_gem_execbuffer.c    |  2 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c           |  2 +-
 drivers/gpu/drm/i915/i915_gem_gtt.h           |  8 +--
 drivers/gpu/drm/i915/selftests/huge_pages.c   |  2 +-
 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c |  6 +--
 11 files changed, 55 insertions(+), 52 deletions(-)

--
2.17.1


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[PATCH 1/3] drm/i915: Mark up GTT sizes as u64

Timo Aaltonen-6
From: Chris Wilson <[hidden email]>

BugLink: https://bugs.launchpad.net/bugs/1815172

Since we use a 64b virtual GTT irrespective of the system, we want to
ensure that the GTT computations remains 64b even on 32b systems,
including treatment of huge virtual pages.

No code generation changes on 64b:

Reported-by: Sergii Romantsov <[hidden email]>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108282
Signed-off-by: Chris Wilson <[hidden email]>
Cc: Joonas Lahtinen <[hidden email]>
Cc: [hidden email]
Reviewed-by: Matthew Auld <[hidden email]>
Link: https://patchwork.freedesktop.org/patch/msgid/20181025091823.20571-1-chris@...
(backported from commit 9125963a9494253fa5a29cc1b4169885d2be7042)
Signed-off-by: Timo Aaltonen <[hidden email]>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c           | 2 +-
 drivers/gpu/drm/i915/i915_gem_gtt.h           | 6 +++---
 drivers/gpu/drm/i915/selftests/huge_pages.c   | 2 +-
 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 6 +++---
 4 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 1f0ac050ad10..01ea8026d764 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1666,7 +1666,7 @@ static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
  if (!found)
  continue;
 
- seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
+ seq_printf(m, "\t\t0x%llx [%03d,%04d]: =", va, pde, pte);
  for (i = 0; i < 4; i++) {
  if (pt_vaddr[pte + i] != scratch_pte)
  seq_printf(m, " %08x", pt_vaddr[pte + i]);
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 7684d15ca83f..97b32caf4c25 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -42,9 +42,9 @@
 #include "i915_gem_request.h"
 #include "i915_selftest.h"
 
-#define I915_GTT_PAGE_SIZE_4K BIT(12)
-#define I915_GTT_PAGE_SIZE_64K BIT(16)
-#define I915_GTT_PAGE_SIZE_2M BIT(21)
+#define I915_GTT_PAGE_SIZE_4K BIT_ULL(12)
+#define I915_GTT_PAGE_SIZE_64K BIT_ULL(16)
+#define I915_GTT_PAGE_SIZE_2M BIT_ULL(21)
 
 #define I915_GTT_PAGE_SIZE I915_GTT_PAGE_SIZE_4K
 #define I915_GTT_MAX_PAGE_SIZE I915_GTT_PAGE_SIZE_2M
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c
index 5cc8101bb2b1..7403bca38d1d 100644
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -548,7 +548,7 @@ static int igt_mock_ppgtt_misaligned_dma(void *arg)
  err = igt_check_page_sizes(vma);
 
  if (vma->page_sizes.gtt != I915_GTT_PAGE_SIZE_4K) {
- pr_err("page_sizes.gtt=%u, expected %lu\n",
+ pr_err("page_sizes.gtt=%u, expected %llu\n",
        vma->page_sizes.gtt, I915_GTT_PAGE_SIZE_4K);
  err = -EINVAL;
  }
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index abfbafa765fc..ed2bdf1ccb51 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -1208,7 +1208,7 @@ static int igt_gtt_reserve(void *arg)
  GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
  if (vma->node.start != total ||
     vma->node.size != 2*I915_GTT_PAGE_SIZE) {
- pr_err("i915_gem_gtt_reserve (pass 1) placement failed, found (%llx + %llx), expected (%llx + %lx)\n",
+ pr_err("i915_gem_gtt_reserve (pass 1) placement failed, found (%llx + %llx), expected (%llx + %llx)\n",
        vma->node.start, vma->node.size,
        total, 2*I915_GTT_PAGE_SIZE);
  err = -EINVAL;
@@ -1257,7 +1257,7 @@ static int igt_gtt_reserve(void *arg)
  GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
  if (vma->node.start != total ||
     vma->node.size != 2*I915_GTT_PAGE_SIZE) {
- pr_err("i915_gem_gtt_reserve (pass 2) placement failed, found (%llx + %llx), expected (%llx + %lx)\n",
+ pr_err("i915_gem_gtt_reserve (pass 2) placement failed, found (%llx + %llx), expected (%llx + %llx)\n",
        vma->node.start, vma->node.size,
        total, 2*I915_GTT_PAGE_SIZE);
  err = -EINVAL;
@@ -1301,7 +1301,7 @@ static int igt_gtt_reserve(void *arg)
  GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
  if (vma->node.start != offset ||
     vma->node.size != 2*I915_GTT_PAGE_SIZE) {
- pr_err("i915_gem_gtt_reserve (pass 3) placement failed, found (%llx + %llx), expected (%llx + %lx)\n",
+ pr_err("i915_gem_gtt_reserve (pass 3) placement failed, found (%llx + %llx), expected (%llx + %llx)\n",
        vma->node.start, vma->node.size,
        offset, 2*I915_GTT_PAGE_SIZE);
  err = -EINVAL;
--
2.17.1


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[PATCH 2/3] drm/i915/gvt: Use I915_GTT_PAGE_SIZE

Timo Aaltonen-6
In reply to this post by Timo Aaltonen-6
From: Zhi Wang <[hidden email]>

BugLink: https://bugs.launchpad.net/bugs/1815172

As there is already an I915_GTT_PAGE_SIZE marco in i915, let GVT-g use it
as well. Also this patch re-names some GTT marcos with additional prefix.

Signed-off-by: Zhi Wang <[hidden email]>
(backported from commit 9556e118889293f6d5d226b64688ee2adfd8964c)
Signed-off-by: Timo Aaltonen <[hidden email]>
---
 drivers/gpu/drm/i915/gvt/cmd_parser.c | 13 +++----
 drivers/gpu/drm/i915/gvt/execlist.c   |  2 +-
 drivers/gpu/drm/i915/gvt/gtt.c        | 51 ++++++++++++++-------------
 drivers/gpu/drm/i915/gvt/gtt.h        |  7 ++--
 drivers/gpu/drm/i915/gvt/reg.h        |  3 +-
 drivers/gpu/drm/i915/gvt/scheduler.c  | 12 +++----
 6 files changed, 45 insertions(+), 43 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index f2bc6fbbf26e..0b4b60fd3a87 100644
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -1378,7 +1378,7 @@ static inline int cmd_address_audit(struct parser_exec_state *s,
  }
 
  if (index_mode) {
- if (guest_gma >= GTT_PAGE_SIZE / sizeof(u64)) {
+ if (guest_gma >= I915_GTT_PAGE_SIZE / sizeof(u64)) {
  ret = -EINVAL;
  goto err;
  }
@@ -1545,10 +1545,10 @@ static int copy_gma_to_hva(struct intel_vgpu *vgpu, struct intel_vgpu_mm *mm,
  return -EFAULT;
  }
 
- offset = gma & (GTT_PAGE_SIZE - 1);
+ offset = gma & (I915_GTT_PAGE_SIZE - 1);
 
- copy_len = (end_gma - gma) >= (GTT_PAGE_SIZE - offset) ?
- GTT_PAGE_SIZE - offset : end_gma - gma;
+ copy_len = (end_gma - gma) >= (I915_GTT_PAGE_SIZE - offset) ?
+ I915_GTT_PAGE_SIZE - offset : end_gma - gma;
 
  intel_gvt_hypervisor_read_gpa(vgpu, gpa, va + len, copy_len);
 
@@ -2516,7 +2516,7 @@ static int scan_workload(struct intel_vgpu_workload *workload)
  int ret = 0;
 
  /* ring base is page aligned */
- if (WARN_ON(!IS_ALIGNED(workload->rb_start, GTT_PAGE_SIZE)))
+ if (WARN_ON(!IS_ALIGNED(workload->rb_start, I915_GTT_PAGE_SIZE)))
  return -EINVAL;
 
  gma_head = workload->rb_start + workload->rb_head;
@@ -2565,7 +2565,8 @@ static int scan_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
  wa_ctx);
 
  /* ring base is page aligned */
- if (WARN_ON(!IS_ALIGNED(wa_ctx->indirect_ctx.guest_gma, GTT_PAGE_SIZE)))
+ if (WARN_ON(!IS_ALIGNED(wa_ctx->indirect_ctx.guest_gma,
+ I915_GTT_PAGE_SIZE)))
  return -EINVAL;
 
  ring_tail = wa_ctx->indirect_ctx.size + 3 * sizeof(uint32_t);
diff --git a/drivers/gpu/drm/i915/gvt/execlist.c b/drivers/gpu/drm/i915/gvt/execlist.c
index 940cdaaa3f24..e2d46a3bda59 100644
--- a/drivers/gpu/drm/i915/gvt/execlist.c
+++ b/drivers/gpu/drm/i915/gvt/execlist.c
@@ -667,7 +667,7 @@ static int submit_context(struct intel_vgpu *vgpu, int ring_id,
  int ret;
 
  ring_context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
- (u32)((desc->lrca + 1) << GTT_PAGE_SHIFT));
+ (u32)((desc->lrca + 1) << I915_GTT_PAGE_SHIFT));
  if (ring_context_gpa == INTEL_GVT_INVALID_ADDR) {
  gvt_vgpu_err("invalid guest context LRCA: %x\n", desc->lrca);
  return -EINVAL;
diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index 64d67ff9bf08..7a1e64ed2a92 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -94,12 +94,12 @@ int intel_gvt_ggtt_index_g2h(struct intel_vgpu *vgpu, unsigned long g_index,
  u64 h_addr;
  int ret;
 
- ret = intel_gvt_ggtt_gmadr_g2h(vgpu, g_index << GTT_PAGE_SHIFT,
+ ret = intel_gvt_ggtt_gmadr_g2h(vgpu, g_index << I915_GTT_PAGE_SHIFT,
        &h_addr);
  if (ret)
  return ret;
 
- *h_index = h_addr >> GTT_PAGE_SHIFT;
+ *h_index = h_addr >> I915_GTT_PAGE_SHIFT;
  return 0;
 }
 
@@ -109,12 +109,12 @@ int intel_gvt_ggtt_h2g_index(struct intel_vgpu *vgpu, unsigned long h_index,
  u64 g_addr;
  int ret;
 
- ret = intel_gvt_ggtt_gmadr_h2g(vgpu, h_index << GTT_PAGE_SHIFT,
+ ret = intel_gvt_ggtt_gmadr_h2g(vgpu, h_index << I915_GTT_PAGE_SHIFT,
        &g_addr);
  if (ret)
  return ret;
 
- *g_index = g_addr >> GTT_PAGE_SHIFT;
+ *g_index = g_addr >> I915_GTT_PAGE_SHIFT;
  return 0;
 }
 
@@ -382,7 +382,7 @@ static void gtt_entry_clear_present(struct intel_gvt_gtt_entry *e)
  */
 static unsigned long gma_to_ggtt_pte_index(unsigned long gma)
 {
- unsigned long x = (gma >> GTT_PAGE_SHIFT);
+ unsigned long x = (gma >> I915_GTT_PAGE_SHIFT);
 
  trace_gma_index(__func__, gma, x);
  return x;
@@ -494,7 +494,7 @@ static inline int ppgtt_spt_get_entry(
  return -EINVAL;
 
  ret = ops->get_entry(page_table, e, index, guest,
- spt->guest_page.gfn << GTT_PAGE_SHIFT,
+ spt->guest_page.gfn << I915_GTT_PAGE_SHIFT,
  spt->vgpu);
  if (ret)
  return ret;
@@ -516,7 +516,7 @@ static inline int ppgtt_spt_set_entry(
  return -EINVAL;
 
  return ops->set_entry(page_table, e, index, guest,
- spt->guest_page.gfn << GTT_PAGE_SHIFT,
+ spt->guest_page.gfn << I915_GTT_PAGE_SHIFT,
  spt->vgpu);
 }
 
@@ -634,7 +634,7 @@ static inline int init_shadow_page(struct intel_vgpu *vgpu,
 
  INIT_HLIST_NODE(&p->node);
 
- p->mfn = daddr >> GTT_PAGE_SHIFT;
+ p->mfn = daddr >> I915_GTT_PAGE_SHIFT;
  hash_add(vgpu->gtt.shadow_page_hash_table, &p->node, p->mfn);
  return 0;
 }
@@ -644,7 +644,7 @@ static inline void clean_shadow_page(struct intel_vgpu *vgpu,
 {
  struct device *kdev = &vgpu->gvt->dev_priv->drm.pdev->dev;
 
- dma_unmap_page(kdev, p->mfn << GTT_PAGE_SHIFT, 4096,
+ dma_unmap_page(kdev, p->mfn << I915_GTT_PAGE_SHIFT, 4096,
  PCI_DMA_BIDIRECTIONAL);
 
  if (!hlist_unhashed(&p->node))
@@ -798,7 +798,7 @@ static struct intel_vgpu_ppgtt_spt *ppgtt_find_shadow_page(
  ((spt)->vgpu->gvt->device_info.gtt_entry_size_shift)
 
 #define pt_entries(spt) \
- (GTT_PAGE_SIZE >> pt_entry_size_shift(spt))
+ (I915_GTT_PAGE_SIZE >> pt_entry_size_shift(spt))
 
 #define for_each_present_guest_entry(spt, e, i) \
  for (i = 0; i < pt_entries(spt); i++) \
@@ -1078,8 +1078,8 @@ static int sync_oos_page(struct intel_vgpu *vgpu,
  old.type = new.type = get_entry_type(spt->guest_page_type);
  old.val64 = new.val64 = 0;
 
- for (index = 0; index < (GTT_PAGE_SIZE >> info->gtt_entry_size_shift);
- index++) {
+ for (index = 0; index < (I915_GTT_PAGE_SIZE >>
+ info->gtt_entry_size_shift); index++) {
  ops->get_entry(oos_page->mem, &old, index, false, 0, vgpu);
  ops->get_entry(NULL, &new, index, true,
  oos_page->guest_page->gfn << PAGE_SHIFT, vgpu);
@@ -1132,8 +1132,8 @@ static int attach_oos_page(struct intel_vgpu *vgpu,
  struct intel_gvt *gvt = vgpu->gvt;
  int ret;
 
- ret = intel_gvt_hypervisor_read_gpa(vgpu, gpt->gfn << GTT_PAGE_SHIFT,
- oos_page->mem, GTT_PAGE_SIZE);
+ ret = intel_gvt_hypervisor_read_gpa(vgpu, gpt->gfn << I915_GTT_PAGE_SHIFT,
+ oos_page->mem, I915_GTT_PAGE_SIZE);
  if (ret)
  return ret;
 
@@ -1418,7 +1418,7 @@ static int gen8_mm_alloc_page_table(struct intel_vgpu_mm *mm)
  mm->shadow_page_table = mem + mm->page_table_entry_size;
  } else if (mm->type == INTEL_GVT_MM_GGTT) {
  mm->page_table_entry_cnt =
- (gvt_ggtt_gm_sz(gvt) >> GTT_PAGE_SHIFT);
+ (gvt_ggtt_gm_sz(gvt) >> I915_GTT_PAGE_SHIFT);
  mm->page_table_entry_size = mm->page_table_entry_cnt *
  info->gtt_entry_size;
  mem = vzalloc(mm->page_table_entry_size);
@@ -1740,8 +1740,8 @@ unsigned long intel_vgpu_gma_to_gpa(struct intel_vgpu_mm *mm, unsigned long gma)
  gma_ops->gma_to_ggtt_pte_index(gma));
  if (ret)
  goto err;
- gpa = (pte_ops->get_pfn(&e) << GTT_PAGE_SHIFT)
- + (gma & ~GTT_PAGE_MASK);
+ gpa = (pte_ops->get_pfn(&e) << I915_GTT_PAGE_SHIFT)
+ + (gma & ~I915_GTT_PAGE_MASK);
 
  trace_gma_translate(vgpu->id, "ggtt", 0, 0, gma, gpa);
  return gpa;
@@ -1793,8 +1793,8 @@ unsigned long intel_vgpu_gma_to_gpa(struct intel_vgpu_mm *mm, unsigned long gma)
  }
  }
 
- gpa = (pte_ops->get_pfn(&e) << GTT_PAGE_SHIFT)
- + (gma & ~GTT_PAGE_MASK);
+ gpa = (pte_ops->get_pfn(&e) << I915_GTT_PAGE_SHIFT)
+ + (gma & ~I915_GTT_PAGE_MASK);
 
  trace_gma_translate(vgpu->id, "ppgtt", 0,
  mm->page_table_level, gma, gpa);
@@ -1862,7 +1862,7 @@ static int emulate_gtt_mmio_write(struct intel_vgpu *vgpu, unsigned int off,
  if (bytes != 4 && bytes != 8)
  return -EINVAL;
 
- gma = g_gtt_index << GTT_PAGE_SHIFT;
+ gma = g_gtt_index << I915_GTT_PAGE_SHIFT;
 
  /* the VM may configure the whole GM space when ballooning is used */
  if (!vgpu_gmadr_is_valid(vgpu, gma))
@@ -1925,7 +1925,7 @@ static int alloc_scratch_pages(struct intel_vgpu *vgpu,
 {
  struct intel_vgpu_gtt *gtt = &vgpu->gtt;
  struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
- int page_entry_num = GTT_PAGE_SIZE >>
+ int page_entry_num = I915_GTT_PAGE_SIZE >>
  vgpu->gvt->device_info.gtt_entry_size_shift;
  void *scratch_pt;
  int i;
@@ -1949,7 +1949,7 @@ static int alloc_scratch_pages(struct intel_vgpu *vgpu,
  return -ENOMEM;
  }
  gtt->scratch_pt[type].page_mfn =
- (unsigned long)(daddr >> GTT_PAGE_SHIFT);
+ (unsigned long)(daddr >> I915_GTT_PAGE_SHIFT);
  gtt->scratch_pt[type].page = virt_to_page(scratch_pt);
  gvt_dbg_mm("vgpu%d create scratch_pt: type %d mfn=0x%lx\n",
  vgpu->id, type, gtt->scratch_pt[type].page_mfn);
@@ -1992,7 +1992,7 @@ static int release_scratch_page_tree(struct intel_vgpu *vgpu)
  for (i = GTT_TYPE_PPGTT_PTE_PT; i < GTT_TYPE_MAX; i++) {
  if (vgpu->gtt.scratch_pt[i].page != NULL) {
  daddr = (dma_addr_t)(vgpu->gtt.scratch_pt[i].page_mfn <<
- GTT_PAGE_SHIFT);
+ I915_GTT_PAGE_SHIFT);
  dma_unmap_page(dev, daddr, 4096, PCI_DMA_BIDIRECTIONAL);
  __free_page(vgpu->gtt.scratch_pt[i].page);
  vgpu->gtt.scratch_pt[i].page = NULL;
@@ -2289,7 +2289,8 @@ int intel_gvt_init_gtt(struct intel_gvt *gvt)
  return -ENOMEM;
  }
  gvt->gtt.scratch_ggtt_page = virt_to_page(page);
- gvt->gtt.scratch_ggtt_mfn = (unsigned long)(daddr >> GTT_PAGE_SHIFT);
+ gvt->gtt.scratch_ggtt_mfn = (unsigned long)(daddr >>
+ I915_GTT_PAGE_SHIFT);
 
  if (enable_out_of_sync) {
  ret = setup_spt_oos(gvt);
@@ -2316,7 +2317,7 @@ void intel_gvt_clean_gtt(struct intel_gvt *gvt)
 {
  struct device *dev = &gvt->dev_priv->drm.pdev->dev;
  dma_addr_t daddr = (dma_addr_t)(gvt->gtt.scratch_ggtt_mfn <<
- GTT_PAGE_SHIFT);
+ I915_GTT_PAGE_SHIFT);
 
  dma_unmap_page(dev, daddr, 4096, PCI_DMA_BIDIRECTIONAL);
 
diff --git a/drivers/gpu/drm/i915/gvt/gtt.h b/drivers/gpu/drm/i915/gvt/gtt.h
index 30a4c8d16026..56255379cd27 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.h
+++ b/drivers/gpu/drm/i915/gvt/gtt.h
@@ -34,9 +34,8 @@
 #ifndef _GVT_GTT_H_
 #define _GVT_GTT_H_
 
-#define GTT_PAGE_SHIFT 12
-#define GTT_PAGE_SIZE (1UL << GTT_PAGE_SHIFT)
-#define GTT_PAGE_MASK (~(GTT_PAGE_SIZE-1))
+#define I915_GTT_PAGE_SHIFT         12
+#define I915_GTT_PAGE_MASK (~(I915_GTT_PAGE_SIZE - 1))
 
 struct intel_vgpu_mm;
 
@@ -243,7 +242,7 @@ struct intel_vgpu_oos_page {
  struct list_head list;
  struct list_head vm_list;
  int id;
- unsigned char mem[GTT_PAGE_SIZE];
+ unsigned char mem[I915_GTT_PAGE_SIZE];
 };
 
 #define GTT_ENTRY_NUM_IN_ONE_PAGE 512
diff --git a/drivers/gpu/drm/i915/gvt/reg.h b/drivers/gpu/drm/i915/gvt/reg.h
index 7d01c77a0f7a..a6a08268aa53 100644
--- a/drivers/gpu/drm/i915/gvt/reg.h
+++ b/drivers/gpu/drm/i915/gvt/reg.h
@@ -71,6 +71,7 @@
 #define RB_HEAD_OFF_MASK ((1U << 21) - (1U << 2))
 #define RB_TAIL_OFF_MASK ((1U << 21) - (1U << 3))
 #define RB_TAIL_SIZE_MASK ((1U << 21) - (1U << 12))
-#define _RING_CTL_BUF_SIZE(ctl) (((ctl) & RB_TAIL_SIZE_MASK) + GTT_PAGE_SIZE)
+#define _RING_CTL_BUF_SIZE(ctl) (((ctl) & RB_TAIL_SIZE_MASK) + \
+ I915_GTT_PAGE_SIZE)
 
 #endif
diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c
index 69f8f0d155b9..618f0f640405 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.c
+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
@@ -81,7 +81,7 @@ static int populate_shadow_context(struct intel_vgpu_workload *workload)
  while (i < context_page_num) {
  context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
  (u32)((workload->ctx_desc.lrca + i) <<
- GTT_PAGE_SHIFT));
+ I915_GTT_PAGE_SHIFT));
  if (context_gpa == INTEL_GVT_INVALID_ADDR) {
  gvt_vgpu_err("Invalid guest context descriptor\n");
  return -EINVAL;
@@ -90,7 +90,7 @@ static int populate_shadow_context(struct intel_vgpu_workload *workload)
  page = i915_gem_object_get_page(ctx_obj, LRC_HEADER_PAGES + i);
  dst = kmap(page);
  intel_gvt_hypervisor_read_gpa(vgpu, context_gpa, dst,
- GTT_PAGE_SIZE);
+ I915_GTT_PAGE_SIZE);
  kunmap(page);
  i++;
  }
@@ -120,7 +120,7 @@ static int populate_shadow_context(struct intel_vgpu_workload *workload)
  sizeof(*shadow_ring_context),
  (void *)shadow_ring_context +
  sizeof(*shadow_ring_context),
- GTT_PAGE_SIZE - sizeof(*shadow_ring_context));
+ I915_GTT_PAGE_SIZE - sizeof(*shadow_ring_context));
 
  kunmap(page);
  return 0;
@@ -483,7 +483,7 @@ static void update_guest_context(struct intel_vgpu_workload *workload)
  while (i < context_page_num) {
  context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
  (u32)((workload->ctx_desc.lrca + i) <<
- GTT_PAGE_SHIFT));
+ I915_GTT_PAGE_SHIFT));
  if (context_gpa == INTEL_GVT_INVALID_ADDR) {
  gvt_vgpu_err("invalid guest context descriptor\n");
  return;
@@ -492,7 +492,7 @@ static void update_guest_context(struct intel_vgpu_workload *workload)
  page = i915_gem_object_get_page(ctx_obj, LRC_HEADER_PAGES + i);
  src = kmap(page);
  intel_gvt_hypervisor_write_gpa(vgpu, context_gpa, src,
- GTT_PAGE_SIZE);
+ I915_GTT_PAGE_SIZE);
  kunmap(page);
  i++;
  }
@@ -517,7 +517,7 @@ static void update_guest_context(struct intel_vgpu_workload *workload)
  sizeof(*shadow_ring_context),
  (void *)shadow_ring_context +
  sizeof(*shadow_ring_context),
- GTT_PAGE_SIZE - sizeof(*shadow_ring_context));
+ I915_GTT_PAGE_SIZE - sizeof(*shadow_ring_context));
 
  kunmap(page);
 }
--
2.17.1


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[PATCH 3/3] drm/i915: Compare user's 64b GTT offset even on 32b

Timo Aaltonen-6
In reply to this post by Timo Aaltonen-6
From: Chris Wilson <[hidden email]>

BugLink: https://bugs.launchpad.net/bugs/1815172

Beware mixing unsigned long constants and 64b values, as on 32b the
constant will be zero extended and discard the high 32b when used as
a mask!

Reported-by: Sergii Romantsov <[hidden email]>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108282
Signed-off-by: Chris Wilson <[hidden email]>
Cc: Joonas Lahtinen <[hidden email]>
Cc: [hidden email]
Reviewed-by: Matthew Auld <[hidden email]>
Link: https://patchwork.freedesktop.org/patch/msgid/20181025091823.20571-2-chris@...
(cherry picked from commit 6fc4e48f9ed46e9adff236a0c350074aafa3b7fa)
Signed-off-by: Timo Aaltonen <[hidden email]>
---
 drivers/gpu/drm/i915/gvt/gtt.h             | 1 -
 drivers/gpu/drm/i915/i915_gem_execbuffer.c | 2 +-
 drivers/gpu/drm/i915/i915_gem_gtt.h        | 2 ++
 3 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/gtt.h b/drivers/gpu/drm/i915/gvt/gtt.h
index 56255379cd27..09e80cb36ec9 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.h
+++ b/drivers/gpu/drm/i915/gvt/gtt.h
@@ -35,7 +35,6 @@
 #define _GVT_GTT_H_
 
 #define I915_GTT_PAGE_SHIFT         12
-#define I915_GTT_PAGE_MASK (~(I915_GTT_PAGE_SIZE - 1))
 
 struct intel_vgpu_mm;
 
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 0d7c1e19a4e3..80e27dfa76c7 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -420,7 +420,7 @@ eb_validate_vma(struct i915_execbuffer *eb,
  * any non-page-aligned or non-canonical addresses.
  */
  if (unlikely(entry->flags & EXEC_OBJECT_PINNED &&
-     entry->offset != gen8_canonical_addr(entry->offset & PAGE_MASK)))
+     entry->offset != gen8_canonical_addr(entry->offset & I915_GTT_PAGE_MASK)))
  return -EINVAL;
 
  /* pad_to_size was once a reserved field, so sanitize it */
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 97b32caf4c25..bd1b0e084f46 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -49,6 +49,8 @@
 #define I915_GTT_PAGE_SIZE I915_GTT_PAGE_SIZE_4K
 #define I915_GTT_MAX_PAGE_SIZE I915_GTT_PAGE_SIZE_2M
 
+#define I915_GTT_PAGE_MASK -I915_GTT_PAGE_SIZE
+
 #define I915_GTT_MIN_ALIGNMENT I915_GTT_PAGE_SIZE
 
 #define I915_FENCE_REG_NONE -1
--
2.17.1


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ACK: [PATCH 0/3] [SRU][Bionic] drm/i915: Fix softpin on 32bit

Khaled Elmously
In reply to this post by Timo Aaltonen-6
On 2019-08-06 22:00:18 , Timo Aaltonen wrote:

> BugLink: https://bugs.launchpad.net/bugs/1815172
>
> We've been carrying a commit reverting softpin support from mesa in bionic,
> because softpin support was broken on 4.15 and 4.18. The patches to fix it
> were sent to stable@ but not all of them got applied to 4.15.x because there
> were minor conflicts. The patch for drm/i915/gvt was added to make the other
> one cherry-pick cleanly.
>
> The reason to get these backported is so that we can drop the revert from
> mesa, because it actually broke Ice Lake which apparently requires softpin
> support in the DRI driver.
>
> Chris Wilson (2):
>   drm/i915: Mark up GTT sizes as u64
>   drm/i915: Compare user's 64b GTT offset even on 32b
>
> Zhi Wang (1):
>   drm/i915/gvt: Use I915_GTT_PAGE_SIZE
>
>  drivers/gpu/drm/i915/gvt/cmd_parser.c         | 13 ++---
>  drivers/gpu/drm/i915/gvt/execlist.c           |  2 +-
>  drivers/gpu/drm/i915/gvt/gtt.c                | 51 ++++++++++---------
>  drivers/gpu/drm/i915/gvt/gtt.h                |  6 +--
>  drivers/gpu/drm/i915/gvt/reg.h                |  3 +-
>  drivers/gpu/drm/i915/gvt/scheduler.c          | 12 ++---
>  drivers/gpu/drm/i915/i915_gem_execbuffer.c    |  2 +-
>  drivers/gpu/drm/i915/i915_gem_gtt.c           |  2 +-
>  drivers/gpu/drm/i915/i915_gem_gtt.h           |  8 +--
>  drivers/gpu/drm/i915/selftests/huge_pages.c   |  2 +-
>  drivers/gpu/drm/i915/selftests/i915_gem_gtt.c |  6 +--
>  11 files changed, 55 insertions(+), 52 deletions(-)
>

Acked-by: Khalid Elmously <[hidden email]>


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ACK: [PATCH 0/3] [SRU][Bionic] drm/i915: Fix softpin on 32bit

Connor Kuehl
In reply to this post by Timo Aaltonen-6
On 8/6/19 12:00 PM, Timo Aaltonen wrote:

> BugLink: https://bugs.launchpad.net/bugs/1815172
>
> We've been carrying a commit reverting softpin support from mesa in bionic,
> because softpin support was broken on 4.15 and 4.18. The patches to fix it
> were sent to stable@ but not all of them got applied to 4.15.x because there
> were minor conflicts. The patch for drm/i915/gvt was added to make the other
> one cherry-pick cleanly.
>
> The reason to get these backported is so that we can drop the revert from
> mesa, because it actually broke Ice Lake which apparently requires softpin
> support in the DRI driver.
>
> Chris Wilson (2):
>   drm/i915: Mark up GTT sizes as u64
>   drm/i915: Compare user's 64b GTT offset even on 32b
>
> Zhi Wang (1):
>   drm/i915/gvt: Use I915_GTT_PAGE_SIZE
>
>  drivers/gpu/drm/i915/gvt/cmd_parser.c         | 13 ++---
>  drivers/gpu/drm/i915/gvt/execlist.c           |  2 +-
>  drivers/gpu/drm/i915/gvt/gtt.c                | 51 ++++++++++---------
>  drivers/gpu/drm/i915/gvt/gtt.h                |  6 +--
>  drivers/gpu/drm/i915/gvt/reg.h                |  3 +-
>  drivers/gpu/drm/i915/gvt/scheduler.c          | 12 ++---
>  drivers/gpu/drm/i915/i915_gem_execbuffer.c    |  2 +-
>  drivers/gpu/drm/i915/i915_gem_gtt.c           |  2 +-
>  drivers/gpu/drm/i915/i915_gem_gtt.h           |  8 +--
>  drivers/gpu/drm/i915/selftests/huge_pages.c   |  2 +-
>  drivers/gpu/drm/i915/selftests/i915_gem_gtt.c |  6 +--
>  11 files changed, 55 insertions(+), 52 deletions(-)
>

Acked-by: Connor Kuehl <[hidden email]>


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APPLIED/cmt: [PATCH 0/3] [SRU][Bionic] drm/i915: Fix softpin on 32bit

Khaled Elmously
In reply to this post by Timo Aaltonen-6
Applied to Bionic.

Timo, note that there was a conflict with patch 2/3.

The first chunk of delta in drivers/gpu/drm/i915/gvt/cmd_parser.c expects the line:



if (guest_gma >= GTT_PAGE_SIZE / sizeof(u64)) {



but in bionic/master-next, that line is actually:


if (guest_gma >= GTT_PAGE_SIZE) {




I went ahead and replaced the line anyway with:
 

if (guest_gma >= I915_GTT_PAGE_SIZE / sizeof(u64)) {



Khaled



On 2019-08-06 22:00:18 , Timo Aaltonen wrote:

> BugLink: https://bugs.launchpad.net/bugs/1815172
>
> We've been carrying a commit reverting softpin support from mesa in bionic,
> because softpin support was broken on 4.15 and 4.18. The patches to fix it
> were sent to stable@ but not all of them got applied to 4.15.x because there
> were minor conflicts. The patch for drm/i915/gvt was added to make the other
> one cherry-pick cleanly.
>
> The reason to get these backported is so that we can drop the revert from
> mesa, because it actually broke Ice Lake which apparently requires softpin
> support in the DRI driver.
>
> Chris Wilson (2):
>   drm/i915: Mark up GTT sizes as u64
>   drm/i915: Compare user's 64b GTT offset even on 32b
>
> Zhi Wang (1):
>   drm/i915/gvt: Use I915_GTT_PAGE_SIZE
>
>  drivers/gpu/drm/i915/gvt/cmd_parser.c         | 13 ++---
>  drivers/gpu/drm/i915/gvt/execlist.c           |  2 +-
>  drivers/gpu/drm/i915/gvt/gtt.c                | 51 ++++++++++---------
>  drivers/gpu/drm/i915/gvt/gtt.h                |  6 +--
>  drivers/gpu/drm/i915/gvt/reg.h                |  3 +-
>  drivers/gpu/drm/i915/gvt/scheduler.c          | 12 ++---
>  drivers/gpu/drm/i915/i915_gem_execbuffer.c    |  2 +-
>  drivers/gpu/drm/i915/i915_gem_gtt.c           |  2 +-
>  drivers/gpu/drm/i915/i915_gem_gtt.h           |  8 +--
>  drivers/gpu/drm/i915/selftests/huge_pages.c   |  2 +-
>  drivers/gpu/drm/i915/selftests/i915_gem_gtt.c |  6 +--
>  11 files changed, 55 insertions(+), 52 deletions(-)
>
> --
> 2.17.1
>
>
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Re: APPLIED/cmt: [PATCH 0/3] [SRU][Bionic] drm/i915: Fix softpin on 32bit

Kleber Souza
On 8/12/19 4:31 AM, Khaled Elmously wrote:

> Applied to Bionic.
>
> Timo, note that there was a conflict with patch 2/3.
>
> The first chunk of delta in drivers/gpu/drm/i915/gvt/cmd_parser.c expects the line:
>
>
>
> if (guest_gma >= GTT_PAGE_SIZE / sizeof(u64)) {
>
>
>
> but in bionic/master-next, that line is actually:
>
>
> if (guest_gma >= GTT_PAGE_SIZE) {
>
>
>
>
> I went ahead and replaced the line anyway with:
>  
>
> if (guest_gma >= I915_GTT_PAGE_SIZE / sizeof(u64)) {

Hi Khaled,

If you make any change when applying a patch from the mailing-list,
please state the reason above your s-o-b line. If we have an issue
with the code in the future we can trace back the changes and
understand the rationale behind it.

The removal of the division for "sizeof(u64)" has been explicitly done
in the meantime with the backport of the following commit applied as
stable update:

drm/i915/gvt: Fix MI_FLUSH_DW parsing with correct index check

which is commit 13bcb80b7ee79431fce361e060611134cb19e209 upstream.

So adding back the division functionally reverts this commit. Also,
it was applied upstream after "drm/i915/gvt: Use I915_GTT_PAGE_SIZE"
and the change it makes is:

        if (index_mode) {
-               if (guest_gma >= I915_GTT_PAGE_SIZE / sizeof(u64)) {
+               if (guest_gma >= I915_GTT_PAGE_SIZE) {
                        ret = -EFAULT;
                        goto err;
                }

so I believe we should stick to what Patch 2/3 does, just replacing
GTT_PAGE_SIZE by I915_GTT_PAGE_SIZE, which end result would be
exactly what's upstream in rev 9556e1188892.

I will amend this commit on master-next to fix it.


Thanks,
Kleber



>
>
>
> Khaled
>
>
>
> On 2019-08-06 22:00:18 , Timo Aaltonen wrote:
>> BugLink: https://bugs.launchpad.net/bugs/1815172
>>
>> We've been carrying a commit reverting softpin support from mesa in bionic,
>> because softpin support was broken on 4.15 and 4.18. The patches to fix it
>> were sent to stable@ but not all of them got applied to 4.15.x because there
>> were minor conflicts. The patch for drm/i915/gvt was added to make the other
>> one cherry-pick cleanly.
>>
>> The reason to get these backported is so that we can drop the revert from
>> mesa, because it actually broke Ice Lake which apparently requires softpin
>> support in the DRI driver.
>>
>> Chris Wilson (2):
>>   drm/i915: Mark up GTT sizes as u64
>>   drm/i915: Compare user's 64b GTT offset even on 32b
>>
>> Zhi Wang (1):
>>   drm/i915/gvt: Use I915_GTT_PAGE_SIZE
>>
>>  drivers/gpu/drm/i915/gvt/cmd_parser.c         | 13 ++---
>>  drivers/gpu/drm/i915/gvt/execlist.c           |  2 +-
>>  drivers/gpu/drm/i915/gvt/gtt.c                | 51 ++++++++++---------
>>  drivers/gpu/drm/i915/gvt/gtt.h                |  6 +--
>>  drivers/gpu/drm/i915/gvt/reg.h                |  3 +-
>>  drivers/gpu/drm/i915/gvt/scheduler.c          | 12 ++---
>>  drivers/gpu/drm/i915/i915_gem_execbuffer.c    |  2 +-
>>  drivers/gpu/drm/i915/i915_gem_gtt.c           |  2 +-
>>  drivers/gpu/drm/i915/i915_gem_gtt.h           |  8 +--
>>  drivers/gpu/drm/i915/selftests/huge_pages.c   |  2 +-
>>  drivers/gpu/drm/i915/selftests/i915_gem_gtt.c |  6 +--
>>  11 files changed, 55 insertions(+), 52 deletions(-)
>>
>> --
>> 2.17.1
>>
>>
>> --
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>> https://lists.ubuntu.com/mailman/listinfo/kernel-team
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Re: APPLIED/cmt: [PATCH 0/3] [SRU][Bionic] drm/i915: Fix softpin on 32bit

Timo Aaltonen-6
On 12.8.2019 11.04, Kleber Souza wrote:

> On 8/12/19 4:31 AM, Khaled Elmously wrote:
>> Applied to Bionic.
>>
>> Timo, note that there was a conflict with patch 2/3.
>>
>> The first chunk of delta in drivers/gpu/drm/i915/gvt/cmd_parser.c expects the line:
>>
>>
>>
>> if (guest_gma >= GTT_PAGE_SIZE / sizeof(u64)) {
>>
>>
>>
>> but in bionic/master-next, that line is actually:
>>
>>
>> if (guest_gma >= GTT_PAGE_SIZE) {
>>
>>
>>
>>
>> I went ahead and replaced the line anyway with:
>>  
>>
>> if (guest_gma >= I915_GTT_PAGE_SIZE / sizeof(u64)) {
>
> Hi Khaled,
>
> If you make any change when applying a patch from the mailing-list,
> please state the reason above your s-o-b line. If we have an issue
> with the code in the future we can trace back the changes and
> understand the rationale behind it.
>
> The removal of the division for "sizeof(u64)" has been explicitly done
> in the meantime with the backport of the following commit applied as
> stable update:
>
> drm/i915/gvt: Fix MI_FLUSH_DW parsing with correct index check
>
> which is commit 13bcb80b7ee79431fce361e060611134cb19e209 upstream.
>
> So adding back the division functionally reverts this commit. Also,
> it was applied upstream after "drm/i915/gvt: Use I915_GTT_PAGE_SIZE"
> and the change it makes is:
>
>         if (index_mode) {
> -               if (guest_gma >= I915_GTT_PAGE_SIZE / sizeof(u64)) {
> +               if (guest_gma >= I915_GTT_PAGE_SIZE) {
>                         ret = -EFAULT;
>                         goto err;
>                 }
>
> so I believe we should stick to what Patch 2/3 does, just replacing
> GTT_PAGE_SIZE by I915_GTT_PAGE_SIZE, which end result would be
> exactly what's upstream in rev 9556e1188892.
>
> I will amend this commit on master-next to fix it.
>
>
> Thanks,
> Kleber

Right, I based these on -56.62 and not master-next, because they were
tested that way. Should work just the same with the new rebase to stable.



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