[PATCH 0/4][Bionic] hisi_sas: Revert and replace SAUCE patches w/ upstream

Previous Topic Next Topic
 
classic Classic list List threaded Threaded
6 messages Options
Reply | Threaded
Open this post in threaded view
|

[PATCH 0/4][Bionic] hisi_sas: Revert and replace SAUCE patches w/ upstream

dann frazier-4
BugLink: https://bugs.launchpad.net/bugs/1762824

We're carrying a couple SAUCE patches for the hisi_sas driver to enable hip08
SoC support. One of the patches is incomplete vs. what landed upstream (module
alias should have been pci, not platform), the other includes extra changes
that didn't land upstream because they are now fixed in firmware.

The upstream patches are clean cherry-picks. Tested on a HiSilicon D06 board.

Xiang Chen (1):
  scsi: hisi_sas: add v3 hw MODULE_DEVICE_TABLE()

Xiaofei Tan (1):
  scsi: hisi_sas: modify some register config for hip08

dann frazier (2):
  Revert "UBUNTU: SAUCE: scsi: hisi_sas: export device table of v3 hw to
    userspace"
  Revert "UBUNTU: SAUCE: scsi: hisi_sas: config for hip08 ES"

 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 25 ++++---------------------
 1 file changed, 4 insertions(+), 21 deletions(-)

--
2.17.0


--
kernel-team mailing list
[hidden email]
https://lists.ubuntu.com/mailman/listinfo/kernel-team
Reply | Threaded
Open this post in threaded view
|

[PATCH 1/4][Bionic] Revert "UBUNTU: SAUCE: scsi: hisi_sas: export device table of v3 hw to userspace"

dann frazier-4
BugLink: https://bugs.launchpad.net/bugs/1762824

Replacing with upstream version.

This reverts commit ba3493d66c3bb443c3c27bcd8f5f2d83e1a9492a.

Signed-off-by: dann frazier <[hidden email]>
---
 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
index d31adc06c0a5..1d536a7a1247 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
@@ -2415,7 +2415,6 @@ static const struct pci_device_id sas_v3_pci_table[] = {
  { PCI_VDEVICE(HUAWEI, 0xa230), hip08 },
  {}
 };
-MODULE_DEVICE_TABLE(pci, sas_v3_pci_table);
 
 static const struct pci_error_handlers hisi_sas_err_handler = {
  .error_detected = hisi_sas_error_detected_v3_hw,
--
2.17.0


--
kernel-team mailing list
[hidden email]
https://lists.ubuntu.com/mailman/listinfo/kernel-team
Reply | Threaded
Open this post in threaded view
|

[PATCH 2/4][Bionic] Revert "UBUNTU: SAUCE: scsi: hisi_sas: config for hip08 ES"

dann frazier-4
In reply to this post by dann frazier-4
BugLink: https://bugs.launchpad.net/bugs/1762824

Replacing with upstream version.

This reverts commit 3aa67d68ce5c0041634e954ee8a4ec611b9b256d.

Signed-off-by: dann frazier <[hidden email]>
---
 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 42 ++++++++------------------
 1 file changed, 13 insertions(+), 29 deletions(-)

diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
index 1d536a7a1247..a1f18689729a 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
@@ -172,7 +172,6 @@
 #define CHL_INT1_MSK (PORT_BASE + 0x1c4)
 #define CHL_INT2_MSK (PORT_BASE + 0x1c8)
 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
-#define SAS_RX_TRAIN_TIMER (PORT_BASE + 0x2a4)
 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
@@ -185,17 +184,6 @@
 #define DMA_RX_STATUS (PORT_BASE + 0x2e8)
 #define DMA_RX_STATUS_BUSY_OFF 0
 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF)
-
-#define COARSETUNE_TIME (PORT_BASE + 0x304)
-#define SAS_TXDEEMPH_G1 (PORT_BASE + 0x350)
-#define SAS_TXDEEMPH_G2 (PORT_BASE + 0x354)
-#define SAS_TXDEEMPH_G3 (PORT_BASE + 0x358)
-#define SAS_TXDEEMPH_G4 (PORT_BASE + 0x35c)
-#define SATA_TXDEEMPH_G1 (PORT_BASE + 0x360)
-#define SATA_TXDEEMPH_G2 (PORT_BASE + 0x364)
-#define SATA_TXDEEMPH_G3 (PORT_BASE + 0x368)
-#define SATA_TXDEEMPH_G4 (PORT_BASE + 0x36c)
-
 #define ERR_CNT_DWS_LOST (PORT_BASE + 0x380)
 #define ERR_CNT_RESET_PROB (PORT_BASE + 0x384)
 #define ERR_CNT_INVLD_DW (PORT_BASE + 0x390)
@@ -414,6 +402,7 @@ static void init_reg_v3_hw(struct hisi_hba *hisi_hba)
  (u32)((1ULL << hisi_hba->queue_count) - 1));
  hisi_sas_write32(hisi_hba, CFG_MAX_TAG, 0xfff0400);
  hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108);
+ hisi_sas_write32(hisi_hba, CFG_1US_TIMER_TRSH, 0xd);
  hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
  hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
  hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
@@ -434,10 +423,10 @@ static void init_reg_v3_hw(struct hisi_hba *hisi_hba)
  hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);
 
  hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
+ hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE, 0x30000);
 
  for (i = 0; i < hisi_hba->n_phy; i++) {
- hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x855);
- hisi_sas_phy_write32(hisi_hba, i, SAS_RX_TRAIN_TIMER, 0x13e80);
+ hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x801);
  hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
  hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
  hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff);
@@ -449,21 +438,16 @@ static void init_reg_v3_hw(struct hisi_hba *hisi_hba)
  hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
  hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
  hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
- hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x1);
-
- /* used for 12G negotiate */
- hisi_sas_phy_write32(hisi_hba, i, COARSETUNE_TIME, 0x1e);
- hisi_sas_phy_write32(hisi_hba, i, SAS_TXDEEMPH_G1, 0x8d04);
- hisi_sas_phy_write32(hisi_hba, i, SAS_TXDEEMPH_G2, 0x8d04);
- hisi_sas_phy_write32(hisi_hba, i, SAS_TXDEEMPH_G3, 0x8d04);
- hisi_sas_phy_write32(hisi_hba, i, SAS_TXDEEMPH_G4, 0x8d04);
- hisi_sas_phy_write32(hisi_hba, i, SATA_TXDEEMPH_G1, 0x8d04);
- hisi_sas_phy_write32(hisi_hba, i, SATA_TXDEEMPH_G2, 0x8d04);
- hisi_sas_phy_write32(hisi_hba, i, SATA_TXDEEMPH_G3, 0x8d04);
- hisi_sas_phy_write32(hisi_hba, i, SATA_TXDEEMPH_G4, 0x8d04);
-
- /* disable stp link timer */
- hisi_sas_phy_write32(hisi_hba, i, STP_LINK_TIMER, 0x2710);
+ hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x0);
+ hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199b4fa);
+ hisi_sas_phy_write32(hisi_hba, i, SAS_SSP_CON_TIMER_CFG,
+     0xa03e8);
+ hisi_sas_phy_write32(hisi_hba, i, SAS_STP_CON_TIMER_CFG,
+     0xa03e8);
+ hisi_sas_phy_write32(hisi_hba, i, STP_LINK_TIMER,
+     0x7f7a120);
+ hisi_sas_phy_write32(hisi_hba, i, CON_CFG_DRIVER,
+     0x2a0a80);
  }
  for (i = 0; i < hisi_hba->queue_count; i++) {
  /* Delivery queue */
--
2.17.0


--
kernel-team mailing list
[hidden email]
https://lists.ubuntu.com/mailman/listinfo/kernel-team
Reply | Threaded
Open this post in threaded view
|

[PATCH 3/4][Bionic] scsi: hisi_sas: modify some register config for hip08

dann frazier-4
In reply to this post by dann frazier-4
From: Xiaofei Tan <[hidden email]>

BugLink: https://bugs.launchpad.net/bugs/1762824

Do some modifications for register configuring for hip08.

In future, to reduce kernel churn with patches to modify registers, any
registers which may change between board models (mostly PHY/SERDES related)
should be set in ACPI reset handler.

Signed-off-by: Xiaofei Tan <[hidden email]>
Signed-off-by: Xiang Chen <[hidden email]>
Signed-off-by: John Garry <[hidden email]>
Signed-off-by: Martin K. Petersen <[hidden email]>
(cherry picked from commit 15c38e31c47c0f2cd7e959054258714991a6a2d6)
Signed-off-by: dann frazier <[hidden email]>
---
 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 23 +++++++++++------------
 1 file changed, 11 insertions(+), 12 deletions(-)

diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
index a1f18689729a..1cfeb6488238 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
@@ -172,6 +172,7 @@
 #define CHL_INT1_MSK (PORT_BASE + 0x1c4)
 #define CHL_INT2_MSK (PORT_BASE + 0x1c8)
 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
+#define SAS_RX_TRAIN_TIMER (PORT_BASE + 0x2a4)
 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
@@ -184,6 +185,8 @@
 #define DMA_RX_STATUS (PORT_BASE + 0x2e8)
 #define DMA_RX_STATUS_BUSY_OFF 0
 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF)
+
+#define COARSETUNE_TIME (PORT_BASE + 0x304)
 #define ERR_CNT_DWS_LOST (PORT_BASE + 0x380)
 #define ERR_CNT_RESET_PROB (PORT_BASE + 0x384)
 #define ERR_CNT_INVLD_DW (PORT_BASE + 0x390)
@@ -423,10 +426,10 @@ static void init_reg_v3_hw(struct hisi_hba *hisi_hba)
  hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);
 
  hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
- hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE, 0x30000);
 
  for (i = 0; i < hisi_hba->n_phy; i++) {
- hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x801);
+ hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x855);
+ hisi_sas_phy_write32(hisi_hba, i, SAS_RX_TRAIN_TIMER, 0x13e80);
  hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
  hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
  hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff);
@@ -438,17 +441,13 @@ static void init_reg_v3_hw(struct hisi_hba *hisi_hba)
  hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
  hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
  hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
- hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x0);
- hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199b4fa);
- hisi_sas_phy_write32(hisi_hba, i, SAS_SSP_CON_TIMER_CFG,
-     0xa03e8);
- hisi_sas_phy_write32(hisi_hba, i, SAS_STP_CON_TIMER_CFG,
-     0xa03e8);
- hisi_sas_phy_write32(hisi_hba, i, STP_LINK_TIMER,
-     0x7f7a120);
- hisi_sas_phy_write32(hisi_hba, i, CON_CFG_DRIVER,
-     0x2a0a80);
+ hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x1);
+ hisi_sas_phy_write32(hisi_hba, i, STP_LINK_TIMER, 0x7f7a120);
+
+ /* used for 12G negotiate */
+ hisi_sas_phy_write32(hisi_hba, i, COARSETUNE_TIME, 0x1e);
  }
+
  for (i = 0; i < hisi_hba->queue_count; i++) {
  /* Delivery queue */
  hisi_sas_write32(hisi_hba,
--
2.17.0


--
kernel-team mailing list
[hidden email]
https://lists.ubuntu.com/mailman/listinfo/kernel-team
Reply | Threaded
Open this post in threaded view
|

[PATCH 4/4][Bionic] scsi: hisi_sas: add v3 hw MODULE_DEVICE_TABLE()

dann frazier-4
In reply to this post by dann frazier-4
From: Xiang Chen <[hidden email]>

BugLink: https://bugs.launchpad.net/bugs/1762824

Export device table of v3 hw to userspace, or auto probe will fail for v3
hw.

Also change the module alias to include "pci", instead of "platform".

Signed-off-by: Xiang Chen <[hidden email]>
Signed-off-by: John Garry <[hidden email]>
Signed-off-by: Martin K. Petersen <[hidden email]>
(cherry picked from commit 40ec66b1bf4352315025b821f7a5aead3d8ea645)
Signed-off-by: dann frazier <[hidden email]>
---
 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
index 1cfeb6488238..30b7bf7c2218 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
@@ -2398,6 +2398,7 @@ static const struct pci_device_id sas_v3_pci_table[] = {
  { PCI_VDEVICE(HUAWEI, 0xa230), hip08 },
  {}
 };
+MODULE_DEVICE_TABLE(pci, sas_v3_pci_table);
 
 static const struct pci_error_handlers hisi_sas_err_handler = {
  .error_detected = hisi_sas_error_detected_v3_hw,
@@ -2420,4 +2421,4 @@ module_pci_driver(sas_v3_pci_driver);
 MODULE_LICENSE("GPL");
 MODULE_AUTHOR("John Garry <[hidden email]>");
 MODULE_DESCRIPTION("HISILICON SAS controller v3 hw driver based on pci device");
-MODULE_ALIAS("platform:" DRV_NAME);
+MODULE_ALIAS("pci:" DRV_NAME);
--
2.17.0


--
kernel-team mailing list
[hidden email]
https://lists.ubuntu.com/mailman/listinfo/kernel-team
Reply | Threaded
Open this post in threaded view
|

APPLIED: [PATCH 0/4][Bionic] hisi_sas: Revert and replace SAUCE patches w/ upstream

Seth Forshee
In reply to this post by dann frazier-4
On Thu, Apr 12, 2018 at 10:44:08AM -0600, dann frazier wrote:
> BugLink: https://bugs.launchpad.net/bugs/1762824
>
> We're carrying a couple SAUCE patches for the hisi_sas driver to enable hip08
> SoC support. One of the patches is incomplete vs. what landed upstream (module
> alias should have been pci, not platform), the other includes extra changes
> that didn't land upstream because they are now fixed in firmware.
>
> The upstream patches are clean cherry-picks. Tested on a HiSilicon D06 board.

Applied to bionic/master-next and unstable/master, thanks!

--
kernel-team mailing list
[hidden email]
https://lists.ubuntu.com/mailman/listinfo/kernel-team