[PATCH 00/10][SRU][G][OEM-5.6] Intel Tiger Lake-H IDs supplement

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[PATCH 00/10][SRU][G][OEM-5.6] Intel Tiger Lake-H IDs supplement

AceLan Kao
BugLink: https://bugs.launchpad.net/bugs/1904521

[Impact]
Intel Tiger Lake-H platform requires new pin settings and IDs to enable.

[Fix]
Intel provides us a list of TGL-H commits from 5.8 and 5.9, we need all of
the commits to enable TGL-H platforms completely.

[Test]
Verified those commits on Intel TGL-H SDP

[Regression potential]
Low, all of those commits are adding new IDs for TGL-H platform.

Alexander Shishkin (1):
  intel_th: pci: Add Tiger Lake PCH-H support

Andy Shevchenko (2):
  mfd: intel-lpss: Add Intel Tiger Lake PCH-H PCI IDs
  pinctrl: intel: Introduce common flags for GPIO mapping scheme

Boris Brezillon (1):
  mtd: spi-nor: Prepare core / manufacturer code split

Guenter Roeck (1):
  mtd: spi-nor: Compile files in controllers/ directory

Heikki Krogerus (1):
  usb: dwc3: pci: add support for the Intel Tiger Lake PCH -H variant

Jarkko Nikula (2):
  i2c: i801: Add support for Intel Tiger Lake PCH-H
  spi: pxa2xx: Add support for Intel Tiger Lake PCH-H

Mika Westerberg (2):
  mtd: spi-nor: intel-spi: Add support for Intel Tiger Lake-H SPI serial
    flash
  pinctrl: tigerlake: Add support for Tiger Lake-H

 drivers/hwtracing/intel_th/pci.c              |   5 +
 drivers/i2c/busses/i2c-i801.c                 |   4 +
 drivers/mfd/intel-lpss-pci.c                  |  16 +
 drivers/mtd/spi-nor/Kconfig                   |  83 +---
 drivers/mtd/spi-nor/Makefile                  |  12 +-
 drivers/mtd/spi-nor/controllers/Kconfig       |  83 ++++
 drivers/mtd/spi-nor/controllers/Makefile      |   9 +
 .../spi-nor/{ => controllers}/aspeed-smc.c    |   0
 .../{ => controllers}/cadence-quadspi.c       |   0
 .../mtd/spi-nor/{ => controllers}/hisi-sfc.c  |   0
 .../spi-nor/{ => controllers}/intel-spi-pci.c |   1 +
 .../{ => controllers}/intel-spi-platform.c    |   0
 .../mtd/spi-nor/{ => controllers}/intel-spi.c |   0
 .../mtd/spi-nor/{ => controllers}/intel-spi.h |   0
 .../spi-nor/{ => controllers}/mtk-quadspi.c   |   0
 .../mtd/spi-nor/{ => controllers}/nxp-spifi.c |   0
 drivers/mtd/spi-nor/{spi-nor.c => core.c}     |   0
 drivers/pinctrl/intel/pinctrl-intel.c         |  19 +-
 drivers/pinctrl/intel/pinctrl-intel.h         |  14 +-
 drivers/pinctrl/intel/pinctrl-tigerlake.c     | 358 ++++++++++++++++++
 drivers/spi/spi-pxa2xx.c                      |   5 +
 drivers/usb/dwc3/dwc3-pci.c                   |   4 +
 22 files changed, 515 insertions(+), 98 deletions(-)
 create mode 100644 drivers/mtd/spi-nor/controllers/Kconfig
 create mode 100644 drivers/mtd/spi-nor/controllers/Makefile
 rename drivers/mtd/spi-nor/{ => controllers}/aspeed-smc.c (100%)
 rename drivers/mtd/spi-nor/{ => controllers}/cadence-quadspi.c (100%)
 rename drivers/mtd/spi-nor/{ => controllers}/hisi-sfc.c (100%)
 rename drivers/mtd/spi-nor/{ => controllers}/intel-spi-pci.c (97%)
 rename drivers/mtd/spi-nor/{ => controllers}/intel-spi-platform.c (100%)
 rename drivers/mtd/spi-nor/{ => controllers}/intel-spi.c (100%)
 rename drivers/mtd/spi-nor/{ => controllers}/intel-spi.h (100%)
 rename drivers/mtd/spi-nor/{ => controllers}/mtk-quadspi.c (100%)
 rename drivers/mtd/spi-nor/{ => controllers}/nxp-spifi.c (100%)
 rename drivers/mtd/spi-nor/{spi-nor.c => core.c} (100%)

--
2.25.1


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[PATCH 01/10][SRU][OEM-5.6] usb: dwc3: pci: add support for the Intel Tiger Lake PCH -H variant

AceLan Kao
From: Heikki Krogerus <[hidden email]>

BugLink: https://bugs.launchpad.net/bugs/1904521

This patch adds the necessary PCI ID for TGP-H devices.

Signed-off-by: Heikki Krogerus <[hidden email]>
Signed-off-by: Felipe Balbi <[hidden email]>
(cherry picked from commit c3f595a8119207cc0f82b3dc6ec5bbf6f3e6b135)
Signed-off-by: AceLan Kao <[hidden email]>
---
 drivers/usb/dwc3/dwc3-pci.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c
index b67372737dc9..41ff052a76d0 100644
--- a/drivers/usb/dwc3/dwc3-pci.c
+++ b/drivers/usb/dwc3/dwc3-pci.c
@@ -38,6 +38,7 @@
 #define PCI_DEVICE_ID_INTEL_ICLLP 0x34ee
 #define PCI_DEVICE_ID_INTEL_EHLLP 0x4b7e
 #define PCI_DEVICE_ID_INTEL_TGPLP 0xa0ee
+#define PCI_DEVICE_ID_INTEL_TGPH 0x43ee
 
 #define PCI_INTEL_BXT_DSM_GUID "732b85d5-b7a7-4a1b-9ba0-4bbd00ffd511"
 #define PCI_INTEL_BXT_FUNC_PMU_PWR 4
@@ -356,6 +357,9 @@ static const struct pci_device_id dwc3_pci_id_table[] = {
  { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGPLP),
   (kernel_ulong_t) &dwc3_pci_intel_properties, },
 
+ { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGPH),
+  (kernel_ulong_t) &dwc3_pci_intel_properties, },
+
  { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_NL_USB),
   (kernel_ulong_t) &dwc3_pci_amd_properties, },
  {  } /* Terminating Entry */
--
2.25.1


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[PATCH 02/10][SRU][OEM-5.6] i2c: i801: Add support for Intel Tiger Lake PCH-H

AceLan Kao
In reply to this post by AceLan Kao
From: Jarkko Nikula <[hidden email]>

BugLink: https://bugs.launchpad.net/bugs/1904521

Add SMBus PCI ID on Intel Tiger Lake PCH-H.

Signed-off-by: Jarkko Nikula <[hidden email]>
Reviewed-by: Jean Delvare <[hidden email]>
Signed-off-by: Wolfram Sang <[hidden email]>
(cherry picked from commit f46efbcad97bfb2caded0397eccce7c71402868c)
Signed-off-by: AceLan Kao <[hidden email]>
---
 drivers/i2c/busses/i2c-i801.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/i2c/busses/i2c-i801.c b/drivers/i2c/busses/i2c-i801.c
index a9c03f5c3482..0b33a5f7ee50 100644
--- a/drivers/i2c/busses/i2c-i801.c
+++ b/drivers/i2c/busses/i2c-i801.c
@@ -67,6 +67,7 @@
  * Comet Lake-H (PCH) 0x06a3 32 hard yes yes yes
  * Elkhart Lake (PCH) 0x4b23 32 hard yes yes yes
  * Tiger Lake-LP (PCH) 0xa0a3 32 hard yes yes yes
+ * Tiger Lake-H (PCH) 0x43a3 32 hard yes yes yes
  * Jasper Lake (SOC) 0x4da3 32 hard yes yes yes
  * Comet Lake-V (PCH) 0xa3a3 32 hard yes yes yes
  *
@@ -221,6 +222,7 @@
 #define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS 0x31d4
 #define PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS 0x34a3
 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
+#define PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS 0x43a3
 #define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS 0x4b23
 #define PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS 0x4da3
 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4
@@ -1074,6 +1076,7 @@ static const struct pci_device_id i801_ids[] = {
  { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS) },
  { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS) },
  { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS) },
+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS) },
  { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS) },
  { 0, }
 };
@@ -1742,6 +1745,7 @@ static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
  case PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS:
  case PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS:
  case PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS:
+ case PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS:
  case PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS:
  priv->features |= FEATURE_BLOCK_PROC;
  priv->features |= FEATURE_I2C_BLOCK_READ;
--
2.25.1


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[PATCH 03/10][SRU][OEM-5.6] mfd: intel-lpss: Add Intel Tiger Lake PCH-H PCI IDs

AceLan Kao
In reply to this post by AceLan Kao
From: Andy Shevchenko <[hidden email]>

BugLink: https://bugs.launchpad.net/bugs/1904521

Intel Tiger Lake PCH-H has the same LPSS than Intel Broxton.
Add the new IDs to the list of supported devices.

Signed-off-by: Andy Shevchenko <[hidden email]>
Signed-off-by: Lee Jones <[hidden email]>
(cherry picked from commit bb7fcad48d3804d814b97c785514e2d1657e157f)
Signed-off-by: AceLan Kao <[hidden email]>
---
 drivers/mfd/intel-lpss-pci.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/drivers/mfd/intel-lpss-pci.c b/drivers/mfd/intel-lpss-pci.c
index c40a6c7d0cf8..88b32a120db9 100644
--- a/drivers/mfd/intel-lpss-pci.c
+++ b/drivers/mfd/intel-lpss-pci.c
@@ -225,6 +225,22 @@ static const struct pci_device_id intel_lpss_pci_ids[] = {
  { PCI_VDEVICE(INTEL, 0x34ea), (kernel_ulong_t)&bxt_i2c_info },
  { PCI_VDEVICE(INTEL, 0x34eb), (kernel_ulong_t)&bxt_i2c_info },
  { PCI_VDEVICE(INTEL, 0x34fb), (kernel_ulong_t)&spt_info },
+ /* TGL-H */
+ { PCI_VDEVICE(INTEL, 0x43a7), (kernel_ulong_t)&bxt_uart_info },
+ { PCI_VDEVICE(INTEL, 0x43a8), (kernel_ulong_t)&bxt_uart_info },
+ { PCI_VDEVICE(INTEL, 0x43a9), (kernel_ulong_t)&bxt_uart_info },
+ { PCI_VDEVICE(INTEL, 0x43aa), (kernel_ulong_t)&bxt_info },
+ { PCI_VDEVICE(INTEL, 0x43ab), (kernel_ulong_t)&bxt_info },
+ { PCI_VDEVICE(INTEL, 0x43ad), (kernel_ulong_t)&bxt_i2c_info },
+ { PCI_VDEVICE(INTEL, 0x43ae), (kernel_ulong_t)&bxt_i2c_info },
+ { PCI_VDEVICE(INTEL, 0x43d8), (kernel_ulong_t)&bxt_i2c_info },
+ { PCI_VDEVICE(INTEL, 0x43da), (kernel_ulong_t)&bxt_uart_info },
+ { PCI_VDEVICE(INTEL, 0x43e8), (kernel_ulong_t)&bxt_i2c_info },
+ { PCI_VDEVICE(INTEL, 0x43e9), (kernel_ulong_t)&bxt_i2c_info },
+ { PCI_VDEVICE(INTEL, 0x43ea), (kernel_ulong_t)&bxt_i2c_info },
+ { PCI_VDEVICE(INTEL, 0x43eb), (kernel_ulong_t)&bxt_i2c_info },
+ { PCI_VDEVICE(INTEL, 0x43fb), (kernel_ulong_t)&bxt_info },
+ { PCI_VDEVICE(INTEL, 0x43fd), (kernel_ulong_t)&bxt_info },
  /* EHL */
  { PCI_VDEVICE(INTEL, 0x4b28), (kernel_ulong_t)&bxt_uart_info },
  { PCI_VDEVICE(INTEL, 0x4b29), (kernel_ulong_t)&bxt_uart_info },
--
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[PATCH 04/10][SRU][OEM-5.6] spi: pxa2xx: Add support for Intel Tiger Lake PCH-H

AceLan Kao
In reply to this post by AceLan Kao
From: Jarkko Nikula <[hidden email]>

BugLink: https://bugs.launchpad.net/bugs/1904521

Add Intel Tiger Lake PCH-H PCI IDs.

Signed-off-by: Jarkko Nikula <[hidden email]>
Link: https://lore.kernel.org/r/20200625140041.745804-1-jarkko.nikula@...
Signed-off-by: Mark Brown <[hidden email]>
(cherry picked from commit cf961fce30f8269d0c2662c48b2618005b67dfd4)
Signed-off-by: AceLan Kao <[hidden email]>
---
 drivers/spi/spi-pxa2xx.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c
index 5f8eb2589595..8047091951fe 100644
--- a/drivers/spi/spi-pxa2xx.c
+++ b/drivers/spi/spi-pxa2xx.c
@@ -1479,6 +1479,11 @@ static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = {
  { PCI_VDEVICE(INTEL, 0x4daa), LPSS_CNL_SSP },
  { PCI_VDEVICE(INTEL, 0x4dab), LPSS_CNL_SSP },
  { PCI_VDEVICE(INTEL, 0x4dfb), LPSS_CNL_SSP },
+ /* TGL-H */
+ { PCI_VDEVICE(INTEL, 0x43aa), LPSS_CNL_SSP },
+ { PCI_VDEVICE(INTEL, 0x43ab), LPSS_CNL_SSP },
+ { PCI_VDEVICE(INTEL, 0x43fb), LPSS_CNL_SSP },
+ { PCI_VDEVICE(INTEL, 0x43fd), LPSS_CNL_SSP },
  /* APL */
  { PCI_VDEVICE(INTEL, 0x5ac2), LPSS_BXT_SSP },
  { PCI_VDEVICE(INTEL, 0x5ac4), LPSS_BXT_SSP },
--
2.25.1


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[PATCH 05/10][SRU][OEM-5.6] mtd: spi-nor: Prepare core / manufacturer code split

AceLan Kao
In reply to this post by AceLan Kao
From: Boris Brezillon <[hidden email]>

BugLink: https://bugs.launchpad.net/bugs/1904521

Move all SPI NOR controller drivers to a controllers/ sub-directory
so that we only have SPI NOR related source files under
drivers/mtd/spi-nor/.

Rename spi-nor.c into core.c, we are about to split this file in multiple
source files (one per manufacturer, plus one for the SFDP parsing logic).

Signed-off-by: Boris Brezillon <[hidden email]>
Signed-off-by: Tudor Ambarus <[hidden email]>
Reviewed-by: Vignesh Raghavendra <[hidden email]>
(bacported from commit a0900d0195d2dcce464f4109445a788d5860b970)
Signed-off-by: AceLan Kao <[hidden email]>
---
 drivers/mtd/spi-nor/Kconfig                   | 83 +------------------
 drivers/mtd/spi-nor/Makefile                  | 10 +--
 drivers/mtd/spi-nor/controllers/Kconfig       | 83 +++++++++++++++++++
 drivers/mtd/spi-nor/controllers/Makefile      |  9 ++
 .../spi-nor/{ => controllers}/aspeed-smc.c    |  0
 .../{ => controllers}/cadence-quadspi.c       |  0
 .../mtd/spi-nor/{ => controllers}/hisi-sfc.c  |  0
 .../spi-nor/{ => controllers}/intel-spi-pci.c |  0
 .../{ => controllers}/intel-spi-platform.c    |  0
 .../mtd/spi-nor/{ => controllers}/intel-spi.c |  0
 .../mtd/spi-nor/{ => controllers}/intel-spi.h |  0
 .../spi-nor/{ => controllers}/mtk-quadspi.c   |  0
 .../mtd/spi-nor/{ => controllers}/nxp-spifi.c |  0
 drivers/mtd/spi-nor/{spi-nor.c => core.c}     |  0
 14 files changed, 95 insertions(+), 90 deletions(-)
 create mode 100644 drivers/mtd/spi-nor/controllers/Kconfig
 create mode 100644 drivers/mtd/spi-nor/controllers/Makefile
 rename drivers/mtd/spi-nor/{ => controllers}/aspeed-smc.c (100%)
 rename drivers/mtd/spi-nor/{ => controllers}/cadence-quadspi.c (100%)
 rename drivers/mtd/spi-nor/{ => controllers}/hisi-sfc.c (100%)
 rename drivers/mtd/spi-nor/{ => controllers}/intel-spi-pci.c (100%)
 rename drivers/mtd/spi-nor/{ => controllers}/intel-spi-platform.c (100%)
 rename drivers/mtd/spi-nor/{ => controllers}/intel-spi.c (100%)
 rename drivers/mtd/spi-nor/{ => controllers}/intel-spi.h (100%)
 rename drivers/mtd/spi-nor/{ => controllers}/mtk-quadspi.c (100%)
 rename drivers/mtd/spi-nor/{ => controllers}/nxp-spifi.c (100%)
 rename drivers/mtd/spi-nor/{spi-nor.c => core.c} (100%)

diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
index c1eda67d1ad2..6e816eafb312 100644
--- a/drivers/mtd/spi-nor/Kconfig
+++ b/drivers/mtd/spi-nor/Kconfig
@@ -24,87 +24,6 @@ config MTD_SPI_NOR_USE_4K_SECTORS
   Please note that some tools/drivers/filesystems may not work with
   4096 B erase size (e.g. UBIFS requires 15 KiB as a minimum).
 
-config SPI_ASPEED_SMC
- tristate "Aspeed flash controllers in SPI mode"
- depends on ARCH_ASPEED || COMPILE_TEST
- depends on HAS_IOMEM && OF
- help
-  This enables support for the Firmware Memory controller (FMC)
-  in the Aspeed AST2500/AST2400 SoCs when attached to SPI NOR chips,
-  and support for the SPI flash memory controller (SPI) for
-  the host firmware. The implementation only supports SPI NOR.
-
-config SPI_CADENCE_QUADSPI
- tristate "Cadence Quad SPI controller"
- depends on OF && (ARM || ARM64 || COMPILE_TEST)
- help
-  Enable support for the Cadence Quad SPI Flash controller.
-
-  Cadence QSPI is a specialized controller for connecting an SPI
-  Flash over 1/2/4-bit wide bus. Enable this option if you have a
-  device with a Cadence QSPI controller and want to access the
-  Flash as an MTD device.
-
-config SPI_HISI_SFC
- tristate "Hisilicon FMC SPI-NOR Flash Controller(SFC)"
- depends on ARCH_HISI || COMPILE_TEST
- depends on HAS_IOMEM
- help
-  This enables support for HiSilicon FMC SPI-NOR flash controller.
-
-config SPI_MTK_QUADSPI
- tristate "MediaTek Quad SPI controller"
- depends on HAS_IOMEM
- help
-  This enables support for the Quad SPI controller in master mode.
-  This controller does not support generic SPI. It only supports
-  SPI NOR.
-
-config SPI_NXP_SPIFI
- tristate "NXP SPI Flash Interface (SPIFI)"
- depends on OF && (ARCH_LPC18XX || COMPILE_TEST)
- depends on HAS_IOMEM
- help
-  Enable support for the NXP LPC SPI Flash Interface controller.
-
-  SPIFI is a specialized controller for connecting serial SPI
-  Flash. Enable this option if you have a device with a SPIFI
-  controller and want to access the Flash as a mtd device.
-
-config SPI_INTEL_SPI
- tristate
-
-config SPI_INTEL_SPI_PCI
- tristate "Intel PCH/PCU SPI flash PCI driver (DANGEROUS)"
- depends on X86 && PCI
- select SPI_INTEL_SPI
- help
-  This enables PCI support for the Intel PCH/PCU SPI controller in
-  master mode. This controller is present in modern Intel hardware
-  and is used to hold BIOS and other persistent settings. Using
-  this driver it is possible to upgrade BIOS directly from Linux.
-
-  Say N here unless you know what you are doing. Overwriting the
-  SPI flash may render the system unbootable.
-
-  To compile this driver as a module, choose M here: the module
-  will be called intel-spi-pci.
-
-config SPI_INTEL_SPI_PLATFORM
- tristate "Intel PCH/PCU SPI flash platform driver (DANGEROUS)"
- depends on X86
- select SPI_INTEL_SPI
- help
-  This enables platform support for the Intel PCH/PCU SPI
-  controller in master mode. This controller is present in modern
-  Intel hardware and is used to hold BIOS and other persistent
-  settings. Using this driver it is possible to upgrade BIOS
-  directly from Linux.
-
-  Say N here unless you know what you are doing. Overwriting the
-  SPI flash may render the system unbootable.
-
-  To compile this driver as a module, choose M here: the module
-  will be called intel-spi-platform.
+source "drivers/mtd/spi-nor/controllers/Kconfig"
 
 endif # MTD_SPI_NOR
diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile
index 9c5ed03cdc19..d6fc70ab4a32 100644
--- a/drivers/mtd/spi-nor/Makefile
+++ b/drivers/mtd/spi-nor/Makefile
@@ -1,10 +1,4 @@
 # SPDX-License-Identifier: GPL-2.0
+
+spi-nor-objs := core.o
 obj-$(CONFIG_MTD_SPI_NOR) += spi-nor.o
-obj-$(CONFIG_SPI_ASPEED_SMC) += aspeed-smc.o
-obj-$(CONFIG_SPI_CADENCE_QUADSPI) += cadence-quadspi.o
-obj-$(CONFIG_SPI_HISI_SFC) += hisi-sfc.o
-obj-$(CONFIG_SPI_MTK_QUADSPI)    += mtk-quadspi.o
-obj-$(CONFIG_SPI_NXP_SPIFI) += nxp-spifi.o
-obj-$(CONFIG_SPI_INTEL_SPI) += intel-spi.o
-obj-$(CONFIG_SPI_INTEL_SPI_PCI) += intel-spi-pci.o
-obj-$(CONFIG_SPI_INTEL_SPI_PLATFORM) += intel-spi-platform.o
diff --git a/drivers/mtd/spi-nor/controllers/Kconfig b/drivers/mtd/spi-nor/controllers/Kconfig
new file mode 100644
index 000000000000..a02feb201a5b
--- /dev/null
+++ b/drivers/mtd/spi-nor/controllers/Kconfig
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: GPL-2.0-only
+config SPI_ASPEED_SMC
+ tristate "Aspeed flash controllers in SPI mode"
+ depends on ARCH_ASPEED || COMPILE_TEST
+ depends on HAS_IOMEM && OF
+ help
+  This enables support for the Firmware Memory controller (FMC)
+  in the Aspeed AST2500/AST2400 SoCs when attached to SPI NOR chips,
+  and support for the SPI flash memory controller (SPI) for
+  the host firmware. The implementation only supports SPI NOR.
+
+config SPI_CADENCE_QUADSPI
+ tristate "Cadence Quad SPI controller"
+ depends on OF && (ARM || ARM64 || COMPILE_TEST)
+ help
+  Enable support for the Cadence Quad SPI Flash controller.
+
+  Cadence QSPI is a specialized controller for connecting an SPI
+  Flash over 1/2/4-bit wide bus. Enable this option if you have a
+  device with a Cadence QSPI controller and want to access the
+  Flash as an MTD device.
+
+config SPI_HISI_SFC
+ tristate "Hisilicon FMC SPI-NOR Flash Controller(SFC)"
+ depends on ARCH_HISI || COMPILE_TEST
+ depends on HAS_IOMEM
+ help
+  This enables support for HiSilicon FMC SPI-NOR flash controller.
+
+config SPI_MTK_QUADSPI
+ tristate "MediaTek Quad SPI controller"
+ depends on HAS_IOMEM
+ help
+  This enables support for the Quad SPI controller in master mode.
+  This controller does not support generic SPI. It only supports
+  SPI NOR.
+
+config SPI_NXP_SPIFI
+ tristate "NXP SPI Flash Interface (SPIFI)"
+ depends on OF && (ARCH_LPC18XX || COMPILE_TEST)
+ depends on HAS_IOMEM
+ help
+  Enable support for the NXP LPC SPI Flash Interface controller.
+
+  SPIFI is a specialized controller for connecting serial SPI
+  Flash. Enable this option if you have a device with a SPIFI
+  controller and want to access the Flash as a mtd device.
+
+config SPI_INTEL_SPI
+ tristate
+
+config SPI_INTEL_SPI_PCI
+ tristate "Intel PCH/PCU SPI flash PCI driver (DANGEROUS)"
+ depends on X86 && PCI
+ select SPI_INTEL_SPI
+ help
+  This enables PCI support for the Intel PCH/PCU SPI controller in
+  master mode. This controller is present in modern Intel hardware
+  and is used to hold BIOS and other persistent settings. Using
+  this driver it is possible to upgrade BIOS directly from Linux.
+
+  Say N here unless you know what you are doing. Overwriting the
+  SPI flash may render the system unbootable.
+
+  To compile this driver as a module, choose M here: the module
+  will be called intel-spi-pci.
+
+config SPI_INTEL_SPI_PLATFORM
+ tristate "Intel PCH/PCU SPI flash platform driver (DANGEROUS)"
+ depends on X86
+ select SPI_INTEL_SPI
+ help
+  This enables platform support for the Intel PCH/PCU SPI
+  controller in master mode. This controller is present in modern
+  Intel hardware and is used to hold BIOS and other persistent
+  settings. Using this driver it is possible to upgrade BIOS
+  directly from Linux.
+
+  Say N here unless you know what you are doing. Overwriting the
+  SPI flash may render the system unbootable.
+
+  To compile this driver as a module, choose M here: the module
+  will be called intel-spi-platform.
diff --git a/drivers/mtd/spi-nor/controllers/Makefile b/drivers/mtd/spi-nor/controllers/Makefile
new file mode 100644
index 000000000000..66e212c763be
--- /dev/null
+++ b/drivers/mtd/spi-nor/controllers/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_SPI_ASPEED_SMC) += aspeed-smc.o
+obj-$(CONFIG_SPI_CADENCE_QUADSPI) += cadence-quadspi.o
+obj-$(CONFIG_SPI_HISI_SFC) += hisi-sfc.o
+obj-$(CONFIG_SPI_MTK_QUADSPI) += mtk-quadspi.o
+obj-$(CONFIG_SPI_NXP_SPIFI) += nxp-spifi.o
+obj-$(CONFIG_SPI_INTEL_SPI) += intel-spi.o
+obj-$(CONFIG_SPI_INTEL_SPI_PCI) += intel-spi-pci.o
+obj-$(CONFIG_SPI_INTEL_SPI_PLATFORM) += intel-spi-platform.o
diff --git a/drivers/mtd/spi-nor/aspeed-smc.c b/drivers/mtd/spi-nor/controllers/aspeed-smc.c
similarity index 100%
rename from drivers/mtd/spi-nor/aspeed-smc.c
rename to drivers/mtd/spi-nor/controllers/aspeed-smc.c
diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/controllers/cadence-quadspi.c
similarity index 100%
rename from drivers/mtd/spi-nor/cadence-quadspi.c
rename to drivers/mtd/spi-nor/controllers/cadence-quadspi.c
diff --git a/drivers/mtd/spi-nor/hisi-sfc.c b/drivers/mtd/spi-nor/controllers/hisi-sfc.c
similarity index 100%
rename from drivers/mtd/spi-nor/hisi-sfc.c
rename to drivers/mtd/spi-nor/controllers/hisi-sfc.c
diff --git a/drivers/mtd/spi-nor/intel-spi-pci.c b/drivers/mtd/spi-nor/controllers/intel-spi-pci.c
similarity index 100%
rename from drivers/mtd/spi-nor/intel-spi-pci.c
rename to drivers/mtd/spi-nor/controllers/intel-spi-pci.c
diff --git a/drivers/mtd/spi-nor/intel-spi-platform.c b/drivers/mtd/spi-nor/controllers/intel-spi-platform.c
similarity index 100%
rename from drivers/mtd/spi-nor/intel-spi-platform.c
rename to drivers/mtd/spi-nor/controllers/intel-spi-platform.c
diff --git a/drivers/mtd/spi-nor/intel-spi.c b/drivers/mtd/spi-nor/controllers/intel-spi.c
similarity index 100%
rename from drivers/mtd/spi-nor/intel-spi.c
rename to drivers/mtd/spi-nor/controllers/intel-spi.c
diff --git a/drivers/mtd/spi-nor/intel-spi.h b/drivers/mtd/spi-nor/controllers/intel-spi.h
similarity index 100%
rename from drivers/mtd/spi-nor/intel-spi.h
rename to drivers/mtd/spi-nor/controllers/intel-spi.h
diff --git a/drivers/mtd/spi-nor/mtk-quadspi.c b/drivers/mtd/spi-nor/controllers/mtk-quadspi.c
similarity index 100%
rename from drivers/mtd/spi-nor/mtk-quadspi.c
rename to drivers/mtd/spi-nor/controllers/mtk-quadspi.c
diff --git a/drivers/mtd/spi-nor/nxp-spifi.c b/drivers/mtd/spi-nor/controllers/nxp-spifi.c
similarity index 100%
rename from drivers/mtd/spi-nor/nxp-spifi.c
rename to drivers/mtd/spi-nor/controllers/nxp-spifi.c
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/core.c
similarity index 100%
rename from drivers/mtd/spi-nor/spi-nor.c
rename to drivers/mtd/spi-nor/core.c
--
2.25.1


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[PATCH 06/10][SRU][OEM-5.6] mtd: spi-nor: Compile files in controllers/ directory

AceLan Kao
In reply to this post by AceLan Kao
From: Guenter Roeck <[hidden email]>

BugLink: https://bugs.launchpad.net/bugs/1904521

Commit a0900d0195d2 ("mtd: spi-nor: Prepare core / manufacturer code
split") moved various files into a new directory, but did not add the new
directory to its parent directory Makefile. The moved files no longer
build, and affected flash chips no longer instantiate.

Adding the new directory to the parent directory Makefile fixes the
problem.

Fixes: a0900d0195d2 ("mtd: spi-nor: Prepare core / manufacturer code split")
Cc: Boris Brezillon <[hidden email]>
Cc: Tudor Ambarus <[hidden email]>
Signed-off-by: Guenter Roeck <[hidden email]>
Reviewed-by: Boris Brezillon <[hidden email]>
Acked-by: Joel Stanley <[hidden email]>
Reviewed-by: Tudor Ambarus <[hidden email]>
Signed-off-by: Richard Weinberger <[hidden email]>
(cherry picked from commit 2098c564701c0dde76063dd9c5c00a7a1f173541)
Signed-off-by: AceLan Kao <[hidden email]>
---
 drivers/mtd/spi-nor/Makefile | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile
index d6fc70ab4a32..e4d3ddd4e207 100644
--- a/drivers/mtd/spi-nor/Makefile
+++ b/drivers/mtd/spi-nor/Makefile
@@ -2,3 +2,5 @@
 
 spi-nor-objs := core.o
 obj-$(CONFIG_MTD_SPI_NOR) += spi-nor.o
+
+obj-$(CONFIG_MTD_SPI_NOR) += controllers/
--
2.25.1


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[PATCH 07/10][SRU][OEM-5.6] mtd: spi-nor: intel-spi: Add support for Intel Tiger Lake-H SPI serial flash

AceLan Kao
In reply to this post by AceLan Kao
From: Mika Westerberg <[hidden email]>

BugLink: https://bugs.launchpad.net/bugs/1904521

Intel Tiger Lake-H has the same SPI serial flash controller as Cannon
Lake. Add Tiger Lake-H PCI ID to the driver list of supported devices.

Signed-off-by: Mika Westerberg <[hidden email]>
Signed-off-by: Tudor Ambarus <[hidden email]>
Link: https://lore.kernel.org/r/20200624192103.78770-1-mika.westerberg@...
(cherry picked from commit a0eec15673222ef52655fc6a5da0008c501aebdc)
Signed-off-by: AceLan Kao <[hidden email]>
---
 drivers/mtd/spi-nor/controllers/intel-spi-pci.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mtd/spi-nor/controllers/intel-spi-pci.c b/drivers/mtd/spi-nor/controllers/intel-spi-pci.c
index 81329f680bec..f3db91acf772 100644
--- a/drivers/mtd/spi-nor/controllers/intel-spi-pci.c
+++ b/drivers/mtd/spi-nor/controllers/intel-spi-pci.c
@@ -69,6 +69,7 @@ static const struct pci_device_id intel_spi_pci_ids[] = {
  { PCI_VDEVICE(INTEL, 0x18e0), (unsigned long)&bxt_info },
  { PCI_VDEVICE(INTEL, 0x19e0), (unsigned long)&bxt_info },
  { PCI_VDEVICE(INTEL, 0x34a4), (unsigned long)&bxt_info },
+ { PCI_VDEVICE(INTEL, 0x43a4), (unsigned long)&cnl_info },
  { PCI_VDEVICE(INTEL, 0x4b24), (unsigned long)&bxt_info },
  { PCI_VDEVICE(INTEL, 0x4da4), (unsigned long)&bxt_info },
  { PCI_VDEVICE(INTEL, 0xa0a4), (unsigned long)&bxt_info },
--
2.25.1


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[PATCH 08/10][SRU][OEM-5.6] pinctrl: intel: Introduce common flags for GPIO mapping scheme

AceLan Kao
In reply to this post by AceLan Kao
From: Andy Shevchenko <[hidden email]>

BugLink: https://bugs.launchpad.net/bugs/1904521

Few drivers are using the same flag to tell Intel pin control core
how to interpret GPIO base.

Provide a generic flags so all drivers can use.

Signed-off-by: Andy Shevchenko <[hidden email]>
Acked-by: Mika Westerberg <[hidden email]>
(cherry picked from commit e5a4ab6a55e2308aad546b594c0d8e5b71d21be9)
Signed-off-by: AceLan Kao <[hidden email]>
---
 drivers/pinctrl/intel/pinctrl-intel.c | 19 +++++++++++++------
 drivers/pinctrl/intel/pinctrl-intel.h | 14 ++++++++++++--
 2 files changed, 25 insertions(+), 8 deletions(-)

diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c
index 74fdfd2b9ff5..a1b286dc7008 100644
--- a/drivers/pinctrl/intel/pinctrl-intel.c
+++ b/drivers/pinctrl/intel/pinctrl-intel.c
@@ -798,7 +798,7 @@ static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned int offset,
  for (j = 0; j < comm->ngpps; j++) {
  const struct intel_padgroup *pgrp = &comm->gpps[j];
 
- if (pgrp->gpio_base < 0)
+ if (pgrp->gpio_base == INTEL_GPIO_BASE_NOMAP)
  continue;
 
  if (offset >= pgrp->gpio_base &&
@@ -1138,7 +1138,7 @@ static int intel_gpio_add_community_ranges(struct intel_pinctrl *pctrl,
  for (i = 0; i < community->ngpps; i++) {
  const struct intel_padgroup *gpp = &community->gpps[i];
 
- if (gpp->gpio_base < 0)
+ if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP)
  continue;
 
  ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
@@ -1180,7 +1180,7 @@ static unsigned int intel_gpio_ngpio(const struct intel_pinctrl *pctrl)
  for (j = 0; j < community->ngpps; j++) {
  const struct intel_padgroup *gpp = &community->gpps[j];
 
- if (gpp->gpio_base < 0)
+ if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP)
  continue;
 
  if (gpp->gpio_base + gpp->size > ngpio)
@@ -1276,8 +1276,15 @@ static int intel_pinctrl_add_padgroups(struct intel_pinctrl *pctrl,
  if (gpps[i].size > 32)
  return -EINVAL;
 
- if (!gpps[i].gpio_base)
- gpps[i].gpio_base = gpps[i].base;
+ /* Special treatment for GPIO base */
+ switch (gpps[i].gpio_base) {
+ case INTEL_GPIO_BASE_MATCH:
+ gpps[i].gpio_base = gpps[i].base;
+ break;
+ case INTEL_GPIO_BASE_NOMAP:
+ default:
+ break;
+ }
 
  gpps[i].padown_num = padown_num;
 
@@ -1596,7 +1603,7 @@ static void intel_restore_hostown(struct intel_pinctrl *pctrl, unsigned int c,
  struct device *dev = pctrl->dev;
  u32 requested;
 
- if (padgrp->gpio_base < 0)
+ if (padgrp->gpio_base == INTEL_GPIO_BASE_NOMAP)
  return;
 
  requested = intel_gpio_is_requested(&pctrl->chip, padgrp->gpio_base, padgrp->size);
diff --git a/drivers/pinctrl/intel/pinctrl-intel.h b/drivers/pinctrl/intel/pinctrl-intel.h
index c6f066f6d3fb..89f38fae6da7 100644
--- a/drivers/pinctrl/intel/pinctrl-intel.h
+++ b/drivers/pinctrl/intel/pinctrl-intel.h
@@ -53,8 +53,7 @@ struct intel_function {
  * @reg_num: GPI_IS register number
  * @base: Starting pin of this group
  * @size: Size of this group (maximum is 32).
- * @gpio_base: Starting GPIO base of this group (%0 if matches with @base,
- *       and %-1 if no GPIO mapping should be created)
+ * @gpio_base: Starting GPIO base of this group
  * @padown_num: PAD_OWN register number (assigned by the core driver)
  *
  * If pad groups of a community are not the same size, use this structure
@@ -68,6 +67,17 @@ struct intel_padgroup {
  unsigned int padown_num;
 };
 
+/**
+ * enum - Special treatment for GPIO base in pad group
+ *
+ * @INTEL_GPIO_BASE_NOMAP: no GPIO mapping should be created
+ * @INTEL_GPIO_BASE_MATCH: matches with starting pin number
+ */
+enum {
+ INTEL_GPIO_BASE_NOMAP = -1,
+ INTEL_GPIO_BASE_MATCH = 0,
+};
+
 /**
  * struct intel_community - Intel pin community description
  * @barno: MMIO BAR number where registers for this community reside
--
2.25.1


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[PATCH 09/10][SRU][OEM-5.6] pinctrl: tigerlake: Add support for Tiger Lake-H

AceLan Kao
In reply to this post by AceLan Kao
From: Mika Westerberg <[hidden email]>

BugLink: https://bugs.launchpad.net/bugs/1904521

Intel Tiger Lake-H has different pin layout than the -LP variant
so add support for this to the existing Tiger Lake driver.

Signed-off-by: Mika Westerberg <[hidden email]>
Signed-off-by: Andy Shevchenko <[hidden email]>
(cherry picked from commit 653d96455e1e30811f4b9ec44d3b9df9bd7a55a3)
Signed-off-by: AceLan Kao <[hidden email]>
---
 drivers/pinctrl/intel/pinctrl-tigerlake.c | 358 ++++++++++++++++++++++
 1 file changed, 358 insertions(+)

diff --git a/drivers/pinctrl/intel/pinctrl-tigerlake.c b/drivers/pinctrl/intel/pinctrl-tigerlake.c
index 08a86f6fdea6..0396a8c82eb6 100644
--- a/drivers/pinctrl/intel/pinctrl-tigerlake.c
+++ b/drivers/pinctrl/intel/pinctrl-tigerlake.c
@@ -382,8 +382,366 @@ static const struct intel_pinctrl_soc_data tgllp_soc_data = {
  .ncommunities = ARRAY_SIZE(tgllp_communities),
 };
 
+/* Tiger Lake-H */
+static const struct pinctrl_pin_desc tglh_pins[] = {
+ /* GPP_A */
+ PINCTRL_PIN(0, "SPI0_IO_2"),
+ PINCTRL_PIN(1, "SPI0_IO_3"),
+ PINCTRL_PIN(2, "SPI0_MOSI_IO_0"),
+ PINCTRL_PIN(3, "SPI0_MISO_IO_1"),
+ PINCTRL_PIN(4, "SPI0_TPM_CSB"),
+ PINCTRL_PIN(5, "SPI0_FLASH_0_CSB"),
+ PINCTRL_PIN(6, "SPI0_FLASH_1_CSB"),
+ PINCTRL_PIN(7, "SPI0_CLK"),
+ PINCTRL_PIN(8, "ESPI_IO_0"),
+ PINCTRL_PIN(9, "ESPI_IO_1"),
+ PINCTRL_PIN(10, "ESPI_IO_2"),
+ PINCTRL_PIN(11, "ESPI_IO_3"),
+ PINCTRL_PIN(12, "ESPI_CS0B"),
+ PINCTRL_PIN(13, "ESPI_CLK"),
+ PINCTRL_PIN(14, "ESPI_RESETB"),
+ PINCTRL_PIN(15, "ESPI_CS1B"),
+ PINCTRL_PIN(16, "ESPI_CS2B"),
+ PINCTRL_PIN(17, "ESPI_CS3B"),
+ PINCTRL_PIN(18, "ESPI_ALERT0B"),
+ PINCTRL_PIN(19, "ESPI_ALERT1B"),
+ PINCTRL_PIN(20, "ESPI_ALERT2B"),
+ PINCTRL_PIN(21, "ESPI_ALERT3B"),
+ PINCTRL_PIN(22, "GPPC_A_14"),
+ PINCTRL_PIN(23, "SPI0_CLK_LOOPBK"),
+ PINCTRL_PIN(24, "ESPI_CLK_LOOPBK"),
+ /* GPP_R */
+ PINCTRL_PIN(25, "HDA_BCLK"),
+ PINCTRL_PIN(26, "HDA_SYNC"),
+ PINCTRL_PIN(27, "HDA_SDO"),
+ PINCTRL_PIN(28, "HDA_SDI_0"),
+ PINCTRL_PIN(29, "HDA_RSTB"),
+ PINCTRL_PIN(30, "HDA_SDI_1"),
+ PINCTRL_PIN(31, "GPP_R_6"),
+ PINCTRL_PIN(32, "GPP_R_7"),
+ PINCTRL_PIN(33, "GPP_R_8"),
+ PINCTRL_PIN(34, "PCIE_LNK_DOWN"),
+ PINCTRL_PIN(35, "ISH_UART0_RTSB"),
+ PINCTRL_PIN(36, "SX_EXIT_HOLDOFFB"),
+ PINCTRL_PIN(37, "CLKOUT_48"),
+ PINCTRL_PIN(38, "ISH_GP_7"),
+ PINCTRL_PIN(39, "ISH_GP_0"),
+ PINCTRL_PIN(40, "ISH_GP_1"),
+ PINCTRL_PIN(41, "ISH_GP_2"),
+ PINCTRL_PIN(42, "ISH_GP_3"),
+ PINCTRL_PIN(43, "ISH_GP_4"),
+ PINCTRL_PIN(44, "ISH_GP_5"),
+ /* GPP_B */
+ PINCTRL_PIN(45, "GSPI0_CS1B"),
+ PINCTRL_PIN(46, "GSPI1_CS1B"),
+ PINCTRL_PIN(47, "VRALERTB"),
+ PINCTRL_PIN(48, "CPU_GP_2"),
+ PINCTRL_PIN(49, "CPU_GP_3"),
+ PINCTRL_PIN(50, "SRCCLKREQB_0"),
+ PINCTRL_PIN(51, "SRCCLKREQB_1"),
+ PINCTRL_PIN(52, "SRCCLKREQB_2"),
+ PINCTRL_PIN(53, "SRCCLKREQB_3"),
+ PINCTRL_PIN(54, "SRCCLKREQB_4"),
+ PINCTRL_PIN(55, "SRCCLKREQB_5"),
+ PINCTRL_PIN(56, "I2S_MCLK"),
+ PINCTRL_PIN(57, "SLP_S0B"),
+ PINCTRL_PIN(58, "PLTRSTB"),
+ PINCTRL_PIN(59, "SPKR"),
+ PINCTRL_PIN(60, "GSPI0_CS0B"),
+ PINCTRL_PIN(61, "GSPI0_CLK"),
+ PINCTRL_PIN(62, "GSPI0_MISO"),
+ PINCTRL_PIN(63, "GSPI0_MOSI"),
+ PINCTRL_PIN(64, "GSPI1_CS0B"),
+ PINCTRL_PIN(65, "GSPI1_CLK"),
+ PINCTRL_PIN(66, "GSPI1_MISO"),
+ PINCTRL_PIN(67, "GSPI1_MOSI"),
+ PINCTRL_PIN(68, "SML1ALERTB"),
+ PINCTRL_PIN(69, "GSPI0_CLK_LOOPBK"),
+ PINCTRL_PIN(70, "GSPI1_CLK_LOOPBK"),
+ /* vGPIO_0 */
+ PINCTRL_PIN(71, "ESPI_USB_OCB_0"),
+ PINCTRL_PIN(72, "ESPI_USB_OCB_1"),
+ PINCTRL_PIN(73, "ESPI_USB_OCB_2"),
+ PINCTRL_PIN(74, "ESPI_USB_OCB_3"),
+ PINCTRL_PIN(75, "USB_CPU_OCB_0"),
+ PINCTRL_PIN(76, "USB_CPU_OCB_1"),
+ PINCTRL_PIN(77, "USB_CPU_OCB_2"),
+ PINCTRL_PIN(78, "USB_CPU_OCB_3"),
+ /* GPP_D */
+ PINCTRL_PIN(79, "SPI1_CSB"),
+ PINCTRL_PIN(80, "SPI1_CLK"),
+ PINCTRL_PIN(81, "SPI1_MISO_IO_1"),
+ PINCTRL_PIN(82, "SPI1_MOSI_IO_0"),
+ PINCTRL_PIN(83, "SML1CLK"),
+ PINCTRL_PIN(84, "I2S2_SFRM"),
+ PINCTRL_PIN(85, "I2S2_TXD"),
+ PINCTRL_PIN(86, "I2S2_RXD"),
+ PINCTRL_PIN(87, "I2S2_SCLK"),
+ PINCTRL_PIN(88, "SML0CLK"),
+ PINCTRL_PIN(89, "SML0DATA"),
+ PINCTRL_PIN(90, "GPP_D_11"),
+ PINCTRL_PIN(91, "ISH_UART0_CTSB"),
+ PINCTRL_PIN(92, "SPI1_IO_2"),
+ PINCTRL_PIN(93, "SPI1_IO_3"),
+ PINCTRL_PIN(94, "SML1DATA"),
+ PINCTRL_PIN(95, "GSPI3_CS0B"),
+ PINCTRL_PIN(96, "GSPI3_CLK"),
+ PINCTRL_PIN(97, "GSPI3_MISO"),
+ PINCTRL_PIN(98, "GSPI3_MOSI"),
+ PINCTRL_PIN(99, "UART3_RXD"),
+ PINCTRL_PIN(100, "UART3_TXD"),
+ PINCTRL_PIN(101, "UART3_RTSB"),
+ PINCTRL_PIN(102, "UART3_CTSB"),
+ PINCTRL_PIN(103, "SPI1_CLK_LOOPBK"),
+ PINCTRL_PIN(104, "GSPI3_CLK_LOOPBK"),
+ /* GPP_C */
+ PINCTRL_PIN(105, "SMBCLK"),
+ PINCTRL_PIN(106, "SMBDATA"),
+ PINCTRL_PIN(107, "SMBALERTB"),
+ PINCTRL_PIN(108, "ISH_UART0_RXD"),
+ PINCTRL_PIN(109, "ISH_UART0_TXD"),
+ PINCTRL_PIN(110, "SML0ALERTB"),
+ PINCTRL_PIN(111, "ISH_I2C2_SDA"),
+ PINCTRL_PIN(112, "ISH_I2C2_SCL"),
+ PINCTRL_PIN(113, "UART0_RXD"),
+ PINCTRL_PIN(114, "UART0_TXD"),
+ PINCTRL_PIN(115, "UART0_RTSB"),
+ PINCTRL_PIN(116, "UART0_CTSB"),
+ PINCTRL_PIN(117, "UART1_RXD"),
+ PINCTRL_PIN(118, "UART1_TXD"),
+ PINCTRL_PIN(119, "UART1_RTSB"),
+ PINCTRL_PIN(120, "UART1_CTSB"),
+ PINCTRL_PIN(121, "I2C0_SDA"),
+ PINCTRL_PIN(122, "I2C0_SCL"),
+ PINCTRL_PIN(123, "I2C1_SDA"),
+ PINCTRL_PIN(124, "I2C1_SCL"),
+ PINCTRL_PIN(125, "UART2_RXD"),
+ PINCTRL_PIN(126, "UART2_TXD"),
+ PINCTRL_PIN(127, "UART2_RTSB"),
+ PINCTRL_PIN(128, "UART2_CTSB"),
+ /* GPP_S */
+ PINCTRL_PIN(129, "SNDW1_CLK"),
+ PINCTRL_PIN(130, "SNDW1_DATA"),
+ PINCTRL_PIN(131, "SNDW2_CLK"),
+ PINCTRL_PIN(132, "SNDW2_DATA"),
+ PINCTRL_PIN(133, "SNDW3_CLK"),
+ PINCTRL_PIN(134, "SNDW3_DATA"),
+ PINCTRL_PIN(135, "SNDW4_CLK"),
+ PINCTRL_PIN(136, "SNDW4_DATA"),
+ /* GPP_G */
+ PINCTRL_PIN(137, "DDPA_CTRLCLK"),
+ PINCTRL_PIN(138, "DDPA_CTRLDATA"),
+ PINCTRL_PIN(139, "DNX_FORCE_RELOAD"),
+ PINCTRL_PIN(140, "GMII_MDC_0"),
+ PINCTRL_PIN(141, "GMII_MDIO_0"),
+ PINCTRL_PIN(142, "SLP_DRAMB"),
+ PINCTRL_PIN(143, "GPPC_G_6"),
+ PINCTRL_PIN(144, "GPPC_G_7"),
+ PINCTRL_PIN(145, "ISH_SPI_CSB"),
+ PINCTRL_PIN(146, "ISH_SPI_CLK"),
+ PINCTRL_PIN(147, "ISH_SPI_MISO"),
+ PINCTRL_PIN(148, "ISH_SPI_MOSI"),
+ PINCTRL_PIN(149, "DDP1_CTRLCLK"),
+ PINCTRL_PIN(150, "DDP1_CTRLDATA"),
+ PINCTRL_PIN(151, "DDP2_CTRLCLK"),
+ PINCTRL_PIN(152, "DDP2_CTRLDATA"),
+ PINCTRL_PIN(153, "GSPI2_CLK_LOOPBK"),
+ /* vGPIO */
+ PINCTRL_PIN(154, "CNV_BTEN"),
+ PINCTRL_PIN(155, "CNV_BT_HOST_WAKEB"),
+ PINCTRL_PIN(156, "CNV_BT_IF_SELECT"),
+ PINCTRL_PIN(157, "vCNV_BT_UART_TXD"),
+ PINCTRL_PIN(158, "vCNV_BT_UART_RXD"),
+ PINCTRL_PIN(159, "vCNV_BT_UART_CTS_B"),
+ PINCTRL_PIN(160, "vCNV_BT_UART_RTS_B"),
+ PINCTRL_PIN(161, "vCNV_MFUART1_TXD"),
+ PINCTRL_PIN(162, "vCNV_MFUART1_RXD"),
+ PINCTRL_PIN(163, "vCNV_MFUART1_CTS_B"),
+ PINCTRL_PIN(164, "vCNV_MFUART1_RTS_B"),
+ PINCTRL_PIN(165, "vUART0_TXD"),
+ PINCTRL_PIN(166, "vUART0_RXD"),
+ PINCTRL_PIN(167, "vUART0_CTS_B"),
+ PINCTRL_PIN(168, "vUART0_RTS_B"),
+ PINCTRL_PIN(169, "vISH_UART0_TXD"),
+ PINCTRL_PIN(170, "vISH_UART0_RXD"),
+ PINCTRL_PIN(171, "vISH_UART0_CTS_B"),
+ PINCTRL_PIN(172, "vISH_UART0_RTS_B"),
+ PINCTRL_PIN(173, "vCNV_BT_I2S_BCLK"),
+ PINCTRL_PIN(174, "vCNV_BT_I2S_WS_SYNC"),
+ PINCTRL_PIN(175, "vCNV_BT_I2S_SDO"),
+ PINCTRL_PIN(176, "vCNV_BT_I2S_SDI"),
+ PINCTRL_PIN(177, "vI2S2_SCLK"),
+ PINCTRL_PIN(178, "vI2S2_SFRM"),
+ PINCTRL_PIN(179, "vI2S2_TXD"),
+ PINCTRL_PIN(180, "vI2S2_RXD"),
+ /* GPP_E */
+ PINCTRL_PIN(181, "SATAXPCIE_0"),
+ PINCTRL_PIN(182, "SATAXPCIE_1"),
+ PINCTRL_PIN(183, "SATAXPCIE_2"),
+ PINCTRL_PIN(184, "CPU_GP_0"),
+ PINCTRL_PIN(185, "SATA_DEVSLP_0"),
+ PINCTRL_PIN(186, "SATA_DEVSLP_1"),
+ PINCTRL_PIN(187, "SATA_DEVSLP_2"),
+ PINCTRL_PIN(188, "CPU_GP_1"),
+ PINCTRL_PIN(189, "SATA_LEDB"),
+ PINCTRL_PIN(190, "USB2_OCB_0"),
+ PINCTRL_PIN(191, "USB2_OCB_1"),
+ PINCTRL_PIN(192, "USB2_OCB_2"),
+ PINCTRL_PIN(193, "USB2_OCB_3"),
+ /* GPP_F */
+ PINCTRL_PIN(194, "SATAXPCIE_3"),
+ PINCTRL_PIN(195, "SATAXPCIE_4"),
+ PINCTRL_PIN(196, "SATAXPCIE_5"),
+ PINCTRL_PIN(197, "SATAXPCIE_6"),
+ PINCTRL_PIN(198, "SATAXPCIE_7"),
+ PINCTRL_PIN(199, "SATA_DEVSLP_3"),
+ PINCTRL_PIN(200, "SATA_DEVSLP_4"),
+ PINCTRL_PIN(201, "SATA_DEVSLP_5"),
+ PINCTRL_PIN(202, "SATA_DEVSLP_6"),
+ PINCTRL_PIN(203, "SATA_DEVSLP_7"),
+ PINCTRL_PIN(204, "SATA_SCLOCK"),
+ PINCTRL_PIN(205, "SATA_SLOAD"),
+ PINCTRL_PIN(206, "SATA_SDATAOUT1"),
+ PINCTRL_PIN(207, "SATA_SDATAOUT0"),
+ PINCTRL_PIN(208, "PS_ONB"),
+ PINCTRL_PIN(209, "M2_SKT2_CFG_0"),
+ PINCTRL_PIN(210, "M2_SKT2_CFG_1"),
+ PINCTRL_PIN(211, "M2_SKT2_CFG_2"),
+ PINCTRL_PIN(212, "M2_SKT2_CFG_3"),
+ PINCTRL_PIN(213, "L_VDDEN"),
+ PINCTRL_PIN(214, "L_BKLTEN"),
+ PINCTRL_PIN(215, "L_BKLTCTL"),
+ PINCTRL_PIN(216, "VNN_CTRL"),
+ PINCTRL_PIN(217, "GPP_F_23"),
+ /* GPP_H */
+ PINCTRL_PIN(218, "SRCCLKREQB_6"),
+ PINCTRL_PIN(219, "SRCCLKREQB_7"),
+ PINCTRL_PIN(220, "SRCCLKREQB_8"),
+ PINCTRL_PIN(221, "SRCCLKREQB_9"),
+ PINCTRL_PIN(222, "SRCCLKREQB_10"),
+ PINCTRL_PIN(223, "SRCCLKREQB_11"),
+ PINCTRL_PIN(224, "SRCCLKREQB_12"),
+ PINCTRL_PIN(225, "SRCCLKREQB_13"),
+ PINCTRL_PIN(226, "SRCCLKREQB_14"),
+ PINCTRL_PIN(227, "SRCCLKREQB_15"),
+ PINCTRL_PIN(228, "SML2CLK"),
+ PINCTRL_PIN(229, "SML2DATA"),
+ PINCTRL_PIN(230, "SML2ALERTB"),
+ PINCTRL_PIN(231, "SML3CLK"),
+ PINCTRL_PIN(232, "SML3DATA"),
+ PINCTRL_PIN(233, "SML3ALERTB"),
+ PINCTRL_PIN(234, "SML4CLK"),
+ PINCTRL_PIN(235, "SML4DATA"),
+ PINCTRL_PIN(236, "SML4ALERTB"),
+ PINCTRL_PIN(237, "ISH_I2C0_SDA"),
+ PINCTRL_PIN(238, "ISH_I2C0_SCL"),
+ PINCTRL_PIN(239, "ISH_I2C1_SDA"),
+ PINCTRL_PIN(240, "ISH_I2C1_SCL"),
+ PINCTRL_PIN(241, "TIME_SYNC_0"),
+ /* GPP_J */
+ PINCTRL_PIN(242, "CNV_PA_BLANKING"),
+ PINCTRL_PIN(243, "CPU_C10_GATEB"),
+ PINCTRL_PIN(244, "CNV_BRI_DT"),
+ PINCTRL_PIN(245, "CNV_BRI_RSP"),
+ PINCTRL_PIN(246, "CNV_RGI_DT"),
+ PINCTRL_PIN(247, "CNV_RGI_RSP"),
+ PINCTRL_PIN(248, "CNV_MFUART2_RXD"),
+ PINCTRL_PIN(249, "CNV_MFUART2_TXD"),
+ PINCTRL_PIN(250, "GPP_J_8"),
+ PINCTRL_PIN(251, "GPP_J_9"),
+ /* GPP_K */
+ PINCTRL_PIN(252, "GSXDOUT"),
+ PINCTRL_PIN(253, "GSXSLOAD"),
+ PINCTRL_PIN(254, "GSXDIN"),
+ PINCTRL_PIN(255, "GSXSRESETB"),
+ PINCTRL_PIN(256, "GSXCLK"),
+ PINCTRL_PIN(257, "ADR_COMPLETE"),
+ PINCTRL_PIN(258, "DDSP_HPD_A"),
+ PINCTRL_PIN(259, "DDSP_HPD_B"),
+ PINCTRL_PIN(260, "CORE_VID_0"),
+ PINCTRL_PIN(261, "CORE_VID_1"),
+ PINCTRL_PIN(262, "DDSP_HPD_C"),
+ PINCTRL_PIN(263, "GPP_K_11"),
+ PINCTRL_PIN(264, "SYS_PWROK"),
+ PINCTRL_PIN(265, "SYS_RESETB"),
+ PINCTRL_PIN(266, "MLK_RSTB"),
+ /* GPP_I */
+ PINCTRL_PIN(267, "PMCALERTB"),
+ PINCTRL_PIN(268, "DDSP_HPD_1"),
+ PINCTRL_PIN(269, "DDSP_HPD_2"),
+ PINCTRL_PIN(270, "DDSP_HPD_3"),
+ PINCTRL_PIN(271, "DDSP_HPD_4"),
+ PINCTRL_PIN(272, "DDPB_CTRLCLK"),
+ PINCTRL_PIN(273, "DDPB_CTRLDATA"),
+ PINCTRL_PIN(274, "DDPC_CTRLCLK"),
+ PINCTRL_PIN(275, "DDPC_CTRLDATA"),
+ PINCTRL_PIN(276, "FUSA_DIAGTEST_EN"),
+ PINCTRL_PIN(277, "FUSA_DIAGTEST_MODE"),
+ PINCTRL_PIN(278, "USB2_OCB_4"),
+ PINCTRL_PIN(279, "USB2_OCB_5"),
+ PINCTRL_PIN(280, "USB2_OCB_6"),
+ PINCTRL_PIN(281, "USB2_OCB_7"),
+ /* JTAG */
+ PINCTRL_PIN(282, "JTAG_TDO"),
+ PINCTRL_PIN(283, "JTAGX"),
+ PINCTRL_PIN(284, "PRDYB"),
+ PINCTRL_PIN(285, "PREQB"),
+ PINCTRL_PIN(286, "JTAG_TDI"),
+ PINCTRL_PIN(287, "JTAG_TMS"),
+ PINCTRL_PIN(288, "JTAG_TCK"),
+ PINCTRL_PIN(289, "DBG_PMODE"),
+ PINCTRL_PIN(290, "CPU_TRSTB"),
+};
+
+static const struct intel_padgroup tglh_community0_gpps[] = {
+ TGL_GPP(0, 0, 24, 0), /* GPP_A */
+ TGL_GPP(1, 25, 44, 128), /* GPP_R */
+ TGL_GPP(2, 45, 70, 32), /* GPP_B */
+ TGL_GPP(3, 71, 78, INTEL_GPIO_BASE_NOMAP), /* vGPIO_0 */
+};
+
+static const struct intel_padgroup tglh_community1_gpps[] = {
+ TGL_GPP(0, 79, 104, 96), /* GPP_D */
+ TGL_GPP(1, 105, 128, 64), /* GPP_C */
+ TGL_GPP(2, 129, 136, 160), /* GPP_S */
+ TGL_GPP(3, 137, 153, 192), /* GPP_G */
+ TGL_GPP(4, 154, 180, 224), /* vGPIO */
+};
+
+static const struct intel_padgroup tglh_community3_gpps[] = {
+ TGL_GPP(0, 181, 193, 256), /* GPP_E */
+ TGL_GPP(1, 194, 217, 288), /* GPP_F */
+};
+
+static const struct intel_padgroup tglh_community4_gpps[] = {
+ TGL_GPP(0, 218, 241, 320), /* GPP_H */
+ TGL_GPP(1, 242, 251, 384), /* GPP_J */
+ TGL_GPP(2, 252, 266, 352), /* GPP_K */
+};
+
+static const struct intel_padgroup tglh_community5_gpps[] = {
+ TGL_GPP(0, 267, 281, 416), /* GPP_I */
+ TGL_GPP(1, 282, 290, INTEL_GPIO_BASE_NOMAP), /* JTAG */
+};
+
+static const struct intel_community tglh_communities[] = {
+ TGL_COMMUNITY(0, 0, 78, tglh_community0_gpps),
+ TGL_COMMUNITY(1, 79, 180, tglh_community1_gpps),
+ TGL_COMMUNITY(2, 181, 217, tglh_community3_gpps),
+ TGL_COMMUNITY(3, 218, 266, tglh_community4_gpps),
+ TGL_COMMUNITY(4, 267, 290, tglh_community5_gpps),
+};
+
+static const struct intel_pinctrl_soc_data tglh_soc_data = {
+ .pins = tglh_pins,
+ .npins = ARRAY_SIZE(tglh_pins),
+ .communities = tglh_communities,
+ .ncommunities = ARRAY_SIZE(tglh_communities),
+};
+
 static const struct acpi_device_id tgl_pinctrl_acpi_match[] = {
  { "INT34C5", (kernel_ulong_t)&tgllp_soc_data },
+ { "INT34C6", (kernel_ulong_t)&tglh_soc_data },
  { }
 };
 MODULE_DEVICE_TABLE(acpi, tgl_pinctrl_acpi_match);
--
2.25.1


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[PATCH 10/10][SRU][OEM-5.6] intel_th: pci: Add Tiger Lake PCH-H support

AceLan Kao
In reply to this post by AceLan Kao
From: Alexander Shishkin <[hidden email]>

BugLink: https://bugs.launchpad.net/bugs/1904521

This adds support for the Trace Hub in Tiger Lake PCH-H.

Signed-off-by: Alexander Shishkin <[hidden email]>
Reviewed-by: Andy Shevchenko <[hidden email]>
Cc: [hidden email] # v4.14+
Link: https://lore.kernel.org/r/20200706161339.55468-3-alexander.shishkin@...
Signed-off-by: Greg Kroah-Hartman <[hidden email]>
(cherry picked from commit 6227585dc7b6a5405fc08dc322f98cb95e2f0eb4)
Signed-off-by: AceLan Kao <[hidden email]>
---
 drivers/hwtracing/intel_th/pci.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/hwtracing/intel_th/pci.c b/drivers/hwtracing/intel_th/pci.c
index 86aa6a46bcba..9e09ce5cc5dd 100644
--- a/drivers/hwtracing/intel_th/pci.c
+++ b/drivers/hwtracing/intel_th/pci.c
@@ -229,6 +229,11 @@ static const struct pci_device_id intel_th_pci_id_table[] = {
  PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xa0a6),
  .driver_data = (kernel_ulong_t)&intel_th_2x,
  },
+ {
+ /* Tiger Lake PCH-H */
+ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x43a6),
+ .driver_data = (kernel_ulong_t)&intel_th_2x,
+ },
  {
  /* Jasper Lake PCH */
  PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4da6),
--
2.25.1


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[PATCH 1/2][SRU][G] mtd: spi-nor: intel-spi: Add support for Intel Tiger Lake-H SPI serial flash

AceLan Kao
In reply to this post by AceLan Kao
From: Mika Westerberg <[hidden email]>

BugLink: https://bugs.launchpad.net/bugs/1904521

Intel Tiger Lake-H has the same SPI serial flash controller as Cannon
Lake. Add Tiger Lake-H PCI ID to the driver list of supported devices.

Signed-off-by: Mika Westerberg <[hidden email]>
Signed-off-by: Tudor Ambarus <[hidden email]>
Link: https://lore.kernel.org/r/20200624192103.78770-1-mika.westerberg@...
(cherry picked from commit a0eec15673222ef52655fc6a5da0008c501aebdc)
Signed-off-by: AceLan Kao <[hidden email]>
---
 drivers/mtd/spi-nor/controllers/intel-spi-pci.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mtd/spi-nor/controllers/intel-spi-pci.c b/drivers/mtd/spi-nor/controllers/intel-spi-pci.c
index 81329f680bec..f3db91acf772 100644
--- a/drivers/mtd/spi-nor/controllers/intel-spi-pci.c
+++ b/drivers/mtd/spi-nor/controllers/intel-spi-pci.c
@@ -69,6 +69,7 @@ static const struct pci_device_id intel_spi_pci_ids[] = {
  { PCI_VDEVICE(INTEL, 0x18e0), (unsigned long)&bxt_info },
  { PCI_VDEVICE(INTEL, 0x19e0), (unsigned long)&bxt_info },
  { PCI_VDEVICE(INTEL, 0x34a4), (unsigned long)&bxt_info },
+ { PCI_VDEVICE(INTEL, 0x43a4), (unsigned long)&cnl_info },
  { PCI_VDEVICE(INTEL, 0x4b24), (unsigned long)&bxt_info },
  { PCI_VDEVICE(INTEL, 0x4da4), (unsigned long)&bxt_info },
  { PCI_VDEVICE(INTEL, 0xa0a4), (unsigned long)&bxt_info },
--
2.25.1


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[PATCH 2/2][SRU][G] pinctrl: tigerlake: Add support for Tiger Lake-H

AceLan Kao
In reply to this post by AceLan Kao
From: Mika Westerberg <[hidden email]>

BugLink: https://bugs.launchpad.net/bugs/1904521

Intel Tiger Lake-H has different pin layout than the -LP variant
so add support for this to the existing Tiger Lake driver.

Signed-off-by: Mika Westerberg <[hidden email]>
Signed-off-by: Andy Shevchenko <[hidden email]>
(cherry picked from commit 653d96455e1e30811f4b9ec44d3b9df9bd7a55a3)
Signed-off-by: AceLan Kao <[hidden email]>
---
 drivers/pinctrl/intel/pinctrl-tigerlake.c | 358 ++++++++++++++++++++++
 1 file changed, 358 insertions(+)

diff --git a/drivers/pinctrl/intel/pinctrl-tigerlake.c b/drivers/pinctrl/intel/pinctrl-tigerlake.c
index bcfd7548e282..8c162dd5f5a1 100644
--- a/drivers/pinctrl/intel/pinctrl-tigerlake.c
+++ b/drivers/pinctrl/intel/pinctrl-tigerlake.c
@@ -380,8 +380,366 @@ static const struct intel_pinctrl_soc_data tgllp_soc_data = {
  .ncommunities = ARRAY_SIZE(tgllp_communities),
 };
 
+/* Tiger Lake-H */
+static const struct pinctrl_pin_desc tglh_pins[] = {
+ /* GPP_A */
+ PINCTRL_PIN(0, "SPI0_IO_2"),
+ PINCTRL_PIN(1, "SPI0_IO_3"),
+ PINCTRL_PIN(2, "SPI0_MOSI_IO_0"),
+ PINCTRL_PIN(3, "SPI0_MISO_IO_1"),
+ PINCTRL_PIN(4, "SPI0_TPM_CSB"),
+ PINCTRL_PIN(5, "SPI0_FLASH_0_CSB"),
+ PINCTRL_PIN(6, "SPI0_FLASH_1_CSB"),
+ PINCTRL_PIN(7, "SPI0_CLK"),
+ PINCTRL_PIN(8, "ESPI_IO_0"),
+ PINCTRL_PIN(9, "ESPI_IO_1"),
+ PINCTRL_PIN(10, "ESPI_IO_2"),
+ PINCTRL_PIN(11, "ESPI_IO_3"),
+ PINCTRL_PIN(12, "ESPI_CS0B"),
+ PINCTRL_PIN(13, "ESPI_CLK"),
+ PINCTRL_PIN(14, "ESPI_RESETB"),
+ PINCTRL_PIN(15, "ESPI_CS1B"),
+ PINCTRL_PIN(16, "ESPI_CS2B"),
+ PINCTRL_PIN(17, "ESPI_CS3B"),
+ PINCTRL_PIN(18, "ESPI_ALERT0B"),
+ PINCTRL_PIN(19, "ESPI_ALERT1B"),
+ PINCTRL_PIN(20, "ESPI_ALERT2B"),
+ PINCTRL_PIN(21, "ESPI_ALERT3B"),
+ PINCTRL_PIN(22, "GPPC_A_14"),
+ PINCTRL_PIN(23, "SPI0_CLK_LOOPBK"),
+ PINCTRL_PIN(24, "ESPI_CLK_LOOPBK"),
+ /* GPP_R */
+ PINCTRL_PIN(25, "HDA_BCLK"),
+ PINCTRL_PIN(26, "HDA_SYNC"),
+ PINCTRL_PIN(27, "HDA_SDO"),
+ PINCTRL_PIN(28, "HDA_SDI_0"),
+ PINCTRL_PIN(29, "HDA_RSTB"),
+ PINCTRL_PIN(30, "HDA_SDI_1"),
+ PINCTRL_PIN(31, "GPP_R_6"),
+ PINCTRL_PIN(32, "GPP_R_7"),
+ PINCTRL_PIN(33, "GPP_R_8"),
+ PINCTRL_PIN(34, "PCIE_LNK_DOWN"),
+ PINCTRL_PIN(35, "ISH_UART0_RTSB"),
+ PINCTRL_PIN(36, "SX_EXIT_HOLDOFFB"),
+ PINCTRL_PIN(37, "CLKOUT_48"),
+ PINCTRL_PIN(38, "ISH_GP_7"),
+ PINCTRL_PIN(39, "ISH_GP_0"),
+ PINCTRL_PIN(40, "ISH_GP_1"),
+ PINCTRL_PIN(41, "ISH_GP_2"),
+ PINCTRL_PIN(42, "ISH_GP_3"),
+ PINCTRL_PIN(43, "ISH_GP_4"),
+ PINCTRL_PIN(44, "ISH_GP_5"),
+ /* GPP_B */
+ PINCTRL_PIN(45, "GSPI0_CS1B"),
+ PINCTRL_PIN(46, "GSPI1_CS1B"),
+ PINCTRL_PIN(47, "VRALERTB"),
+ PINCTRL_PIN(48, "CPU_GP_2"),
+ PINCTRL_PIN(49, "CPU_GP_3"),
+ PINCTRL_PIN(50, "SRCCLKREQB_0"),
+ PINCTRL_PIN(51, "SRCCLKREQB_1"),
+ PINCTRL_PIN(52, "SRCCLKREQB_2"),
+ PINCTRL_PIN(53, "SRCCLKREQB_3"),
+ PINCTRL_PIN(54, "SRCCLKREQB_4"),
+ PINCTRL_PIN(55, "SRCCLKREQB_5"),
+ PINCTRL_PIN(56, "I2S_MCLK"),
+ PINCTRL_PIN(57, "SLP_S0B"),
+ PINCTRL_PIN(58, "PLTRSTB"),
+ PINCTRL_PIN(59, "SPKR"),
+ PINCTRL_PIN(60, "GSPI0_CS0B"),
+ PINCTRL_PIN(61, "GSPI0_CLK"),
+ PINCTRL_PIN(62, "GSPI0_MISO"),
+ PINCTRL_PIN(63, "GSPI0_MOSI"),
+ PINCTRL_PIN(64, "GSPI1_CS0B"),
+ PINCTRL_PIN(65, "GSPI1_CLK"),
+ PINCTRL_PIN(66, "GSPI1_MISO"),
+ PINCTRL_PIN(67, "GSPI1_MOSI"),
+ PINCTRL_PIN(68, "SML1ALERTB"),
+ PINCTRL_PIN(69, "GSPI0_CLK_LOOPBK"),
+ PINCTRL_PIN(70, "GSPI1_CLK_LOOPBK"),
+ /* vGPIO_0 */
+ PINCTRL_PIN(71, "ESPI_USB_OCB_0"),
+ PINCTRL_PIN(72, "ESPI_USB_OCB_1"),
+ PINCTRL_PIN(73, "ESPI_USB_OCB_2"),
+ PINCTRL_PIN(74, "ESPI_USB_OCB_3"),
+ PINCTRL_PIN(75, "USB_CPU_OCB_0"),
+ PINCTRL_PIN(76, "USB_CPU_OCB_1"),
+ PINCTRL_PIN(77, "USB_CPU_OCB_2"),
+ PINCTRL_PIN(78, "USB_CPU_OCB_3"),
+ /* GPP_D */
+ PINCTRL_PIN(79, "SPI1_CSB"),
+ PINCTRL_PIN(80, "SPI1_CLK"),
+ PINCTRL_PIN(81, "SPI1_MISO_IO_1"),
+ PINCTRL_PIN(82, "SPI1_MOSI_IO_0"),
+ PINCTRL_PIN(83, "SML1CLK"),
+ PINCTRL_PIN(84, "I2S2_SFRM"),
+ PINCTRL_PIN(85, "I2S2_TXD"),
+ PINCTRL_PIN(86, "I2S2_RXD"),
+ PINCTRL_PIN(87, "I2S2_SCLK"),
+ PINCTRL_PIN(88, "SML0CLK"),
+ PINCTRL_PIN(89, "SML0DATA"),
+ PINCTRL_PIN(90, "GPP_D_11"),
+ PINCTRL_PIN(91, "ISH_UART0_CTSB"),
+ PINCTRL_PIN(92, "SPI1_IO_2"),
+ PINCTRL_PIN(93, "SPI1_IO_3"),
+ PINCTRL_PIN(94, "SML1DATA"),
+ PINCTRL_PIN(95, "GSPI3_CS0B"),
+ PINCTRL_PIN(96, "GSPI3_CLK"),
+ PINCTRL_PIN(97, "GSPI3_MISO"),
+ PINCTRL_PIN(98, "GSPI3_MOSI"),
+ PINCTRL_PIN(99, "UART3_RXD"),
+ PINCTRL_PIN(100, "UART3_TXD"),
+ PINCTRL_PIN(101, "UART3_RTSB"),
+ PINCTRL_PIN(102, "UART3_CTSB"),
+ PINCTRL_PIN(103, "SPI1_CLK_LOOPBK"),
+ PINCTRL_PIN(104, "GSPI3_CLK_LOOPBK"),
+ /* GPP_C */
+ PINCTRL_PIN(105, "SMBCLK"),
+ PINCTRL_PIN(106, "SMBDATA"),
+ PINCTRL_PIN(107, "SMBALERTB"),
+ PINCTRL_PIN(108, "ISH_UART0_RXD"),
+ PINCTRL_PIN(109, "ISH_UART0_TXD"),
+ PINCTRL_PIN(110, "SML0ALERTB"),
+ PINCTRL_PIN(111, "ISH_I2C2_SDA"),
+ PINCTRL_PIN(112, "ISH_I2C2_SCL"),
+ PINCTRL_PIN(113, "UART0_RXD"),
+ PINCTRL_PIN(114, "UART0_TXD"),
+ PINCTRL_PIN(115, "UART0_RTSB"),
+ PINCTRL_PIN(116, "UART0_CTSB"),
+ PINCTRL_PIN(117, "UART1_RXD"),
+ PINCTRL_PIN(118, "UART1_TXD"),
+ PINCTRL_PIN(119, "UART1_RTSB"),
+ PINCTRL_PIN(120, "UART1_CTSB"),
+ PINCTRL_PIN(121, "I2C0_SDA"),
+ PINCTRL_PIN(122, "I2C0_SCL"),
+ PINCTRL_PIN(123, "I2C1_SDA"),
+ PINCTRL_PIN(124, "I2C1_SCL"),
+ PINCTRL_PIN(125, "UART2_RXD"),
+ PINCTRL_PIN(126, "UART2_TXD"),
+ PINCTRL_PIN(127, "UART2_RTSB"),
+ PINCTRL_PIN(128, "UART2_CTSB"),
+ /* GPP_S */
+ PINCTRL_PIN(129, "SNDW1_CLK"),
+ PINCTRL_PIN(130, "SNDW1_DATA"),
+ PINCTRL_PIN(131, "SNDW2_CLK"),
+ PINCTRL_PIN(132, "SNDW2_DATA"),
+ PINCTRL_PIN(133, "SNDW3_CLK"),
+ PINCTRL_PIN(134, "SNDW3_DATA"),
+ PINCTRL_PIN(135, "SNDW4_CLK"),
+ PINCTRL_PIN(136, "SNDW4_DATA"),
+ /* GPP_G */
+ PINCTRL_PIN(137, "DDPA_CTRLCLK"),
+ PINCTRL_PIN(138, "DDPA_CTRLDATA"),
+ PINCTRL_PIN(139, "DNX_FORCE_RELOAD"),
+ PINCTRL_PIN(140, "GMII_MDC_0"),
+ PINCTRL_PIN(141, "GMII_MDIO_0"),
+ PINCTRL_PIN(142, "SLP_DRAMB"),
+ PINCTRL_PIN(143, "GPPC_G_6"),
+ PINCTRL_PIN(144, "GPPC_G_7"),
+ PINCTRL_PIN(145, "ISH_SPI_CSB"),
+ PINCTRL_PIN(146, "ISH_SPI_CLK"),
+ PINCTRL_PIN(147, "ISH_SPI_MISO"),
+ PINCTRL_PIN(148, "ISH_SPI_MOSI"),
+ PINCTRL_PIN(149, "DDP1_CTRLCLK"),
+ PINCTRL_PIN(150, "DDP1_CTRLDATA"),
+ PINCTRL_PIN(151, "DDP2_CTRLCLK"),
+ PINCTRL_PIN(152, "DDP2_CTRLDATA"),
+ PINCTRL_PIN(153, "GSPI2_CLK_LOOPBK"),
+ /* vGPIO */
+ PINCTRL_PIN(154, "CNV_BTEN"),
+ PINCTRL_PIN(155, "CNV_BT_HOST_WAKEB"),
+ PINCTRL_PIN(156, "CNV_BT_IF_SELECT"),
+ PINCTRL_PIN(157, "vCNV_BT_UART_TXD"),
+ PINCTRL_PIN(158, "vCNV_BT_UART_RXD"),
+ PINCTRL_PIN(159, "vCNV_BT_UART_CTS_B"),
+ PINCTRL_PIN(160, "vCNV_BT_UART_RTS_B"),
+ PINCTRL_PIN(161, "vCNV_MFUART1_TXD"),
+ PINCTRL_PIN(162, "vCNV_MFUART1_RXD"),
+ PINCTRL_PIN(163, "vCNV_MFUART1_CTS_B"),
+ PINCTRL_PIN(164, "vCNV_MFUART1_RTS_B"),
+ PINCTRL_PIN(165, "vUART0_TXD"),
+ PINCTRL_PIN(166, "vUART0_RXD"),
+ PINCTRL_PIN(167, "vUART0_CTS_B"),
+ PINCTRL_PIN(168, "vUART0_RTS_B"),
+ PINCTRL_PIN(169, "vISH_UART0_TXD"),
+ PINCTRL_PIN(170, "vISH_UART0_RXD"),
+ PINCTRL_PIN(171, "vISH_UART0_CTS_B"),
+ PINCTRL_PIN(172, "vISH_UART0_RTS_B"),
+ PINCTRL_PIN(173, "vCNV_BT_I2S_BCLK"),
+ PINCTRL_PIN(174, "vCNV_BT_I2S_WS_SYNC"),
+ PINCTRL_PIN(175, "vCNV_BT_I2S_SDO"),
+ PINCTRL_PIN(176, "vCNV_BT_I2S_SDI"),
+ PINCTRL_PIN(177, "vI2S2_SCLK"),
+ PINCTRL_PIN(178, "vI2S2_SFRM"),
+ PINCTRL_PIN(179, "vI2S2_TXD"),
+ PINCTRL_PIN(180, "vI2S2_RXD"),
+ /* GPP_E */
+ PINCTRL_PIN(181, "SATAXPCIE_0"),
+ PINCTRL_PIN(182, "SATAXPCIE_1"),
+ PINCTRL_PIN(183, "SATAXPCIE_2"),
+ PINCTRL_PIN(184, "CPU_GP_0"),
+ PINCTRL_PIN(185, "SATA_DEVSLP_0"),
+ PINCTRL_PIN(186, "SATA_DEVSLP_1"),
+ PINCTRL_PIN(187, "SATA_DEVSLP_2"),
+ PINCTRL_PIN(188, "CPU_GP_1"),
+ PINCTRL_PIN(189, "SATA_LEDB"),
+ PINCTRL_PIN(190, "USB2_OCB_0"),
+ PINCTRL_PIN(191, "USB2_OCB_1"),
+ PINCTRL_PIN(192, "USB2_OCB_2"),
+ PINCTRL_PIN(193, "USB2_OCB_3"),
+ /* GPP_F */
+ PINCTRL_PIN(194, "SATAXPCIE_3"),
+ PINCTRL_PIN(195, "SATAXPCIE_4"),
+ PINCTRL_PIN(196, "SATAXPCIE_5"),
+ PINCTRL_PIN(197, "SATAXPCIE_6"),
+ PINCTRL_PIN(198, "SATAXPCIE_7"),
+ PINCTRL_PIN(199, "SATA_DEVSLP_3"),
+ PINCTRL_PIN(200, "SATA_DEVSLP_4"),
+ PINCTRL_PIN(201, "SATA_DEVSLP_5"),
+ PINCTRL_PIN(202, "SATA_DEVSLP_6"),
+ PINCTRL_PIN(203, "SATA_DEVSLP_7"),
+ PINCTRL_PIN(204, "SATA_SCLOCK"),
+ PINCTRL_PIN(205, "SATA_SLOAD"),
+ PINCTRL_PIN(206, "SATA_SDATAOUT1"),
+ PINCTRL_PIN(207, "SATA_SDATAOUT0"),
+ PINCTRL_PIN(208, "PS_ONB"),
+ PINCTRL_PIN(209, "M2_SKT2_CFG_0"),
+ PINCTRL_PIN(210, "M2_SKT2_CFG_1"),
+ PINCTRL_PIN(211, "M2_SKT2_CFG_2"),
+ PINCTRL_PIN(212, "M2_SKT2_CFG_3"),
+ PINCTRL_PIN(213, "L_VDDEN"),
+ PINCTRL_PIN(214, "L_BKLTEN"),
+ PINCTRL_PIN(215, "L_BKLTCTL"),
+ PINCTRL_PIN(216, "VNN_CTRL"),
+ PINCTRL_PIN(217, "GPP_F_23"),
+ /* GPP_H */
+ PINCTRL_PIN(218, "SRCCLKREQB_6"),
+ PINCTRL_PIN(219, "SRCCLKREQB_7"),
+ PINCTRL_PIN(220, "SRCCLKREQB_8"),
+ PINCTRL_PIN(221, "SRCCLKREQB_9"),
+ PINCTRL_PIN(222, "SRCCLKREQB_10"),
+ PINCTRL_PIN(223, "SRCCLKREQB_11"),
+ PINCTRL_PIN(224, "SRCCLKREQB_12"),
+ PINCTRL_PIN(225, "SRCCLKREQB_13"),
+ PINCTRL_PIN(226, "SRCCLKREQB_14"),
+ PINCTRL_PIN(227, "SRCCLKREQB_15"),
+ PINCTRL_PIN(228, "SML2CLK"),
+ PINCTRL_PIN(229, "SML2DATA"),
+ PINCTRL_PIN(230, "SML2ALERTB"),
+ PINCTRL_PIN(231, "SML3CLK"),
+ PINCTRL_PIN(232, "SML3DATA"),
+ PINCTRL_PIN(233, "SML3ALERTB"),
+ PINCTRL_PIN(234, "SML4CLK"),
+ PINCTRL_PIN(235, "SML4DATA"),
+ PINCTRL_PIN(236, "SML4ALERTB"),
+ PINCTRL_PIN(237, "ISH_I2C0_SDA"),
+ PINCTRL_PIN(238, "ISH_I2C0_SCL"),
+ PINCTRL_PIN(239, "ISH_I2C1_SDA"),
+ PINCTRL_PIN(240, "ISH_I2C1_SCL"),
+ PINCTRL_PIN(241, "TIME_SYNC_0"),
+ /* GPP_J */
+ PINCTRL_PIN(242, "CNV_PA_BLANKING"),
+ PINCTRL_PIN(243, "CPU_C10_GATEB"),
+ PINCTRL_PIN(244, "CNV_BRI_DT"),
+ PINCTRL_PIN(245, "CNV_BRI_RSP"),
+ PINCTRL_PIN(246, "CNV_RGI_DT"),
+ PINCTRL_PIN(247, "CNV_RGI_RSP"),
+ PINCTRL_PIN(248, "CNV_MFUART2_RXD"),
+ PINCTRL_PIN(249, "CNV_MFUART2_TXD"),
+ PINCTRL_PIN(250, "GPP_J_8"),
+ PINCTRL_PIN(251, "GPP_J_9"),
+ /* GPP_K */
+ PINCTRL_PIN(252, "GSXDOUT"),
+ PINCTRL_PIN(253, "GSXSLOAD"),
+ PINCTRL_PIN(254, "GSXDIN"),
+ PINCTRL_PIN(255, "GSXSRESETB"),
+ PINCTRL_PIN(256, "GSXCLK"),
+ PINCTRL_PIN(257, "ADR_COMPLETE"),
+ PINCTRL_PIN(258, "DDSP_HPD_A"),
+ PINCTRL_PIN(259, "DDSP_HPD_B"),
+ PINCTRL_PIN(260, "CORE_VID_0"),
+ PINCTRL_PIN(261, "CORE_VID_1"),
+ PINCTRL_PIN(262, "DDSP_HPD_C"),
+ PINCTRL_PIN(263, "GPP_K_11"),
+ PINCTRL_PIN(264, "SYS_PWROK"),
+ PINCTRL_PIN(265, "SYS_RESETB"),
+ PINCTRL_PIN(266, "MLK_RSTB"),
+ /* GPP_I */
+ PINCTRL_PIN(267, "PMCALERTB"),
+ PINCTRL_PIN(268, "DDSP_HPD_1"),
+ PINCTRL_PIN(269, "DDSP_HPD_2"),
+ PINCTRL_PIN(270, "DDSP_HPD_3"),
+ PINCTRL_PIN(271, "DDSP_HPD_4"),
+ PINCTRL_PIN(272, "DDPB_CTRLCLK"),
+ PINCTRL_PIN(273, "DDPB_CTRLDATA"),
+ PINCTRL_PIN(274, "DDPC_CTRLCLK"),
+ PINCTRL_PIN(275, "DDPC_CTRLDATA"),
+ PINCTRL_PIN(276, "FUSA_DIAGTEST_EN"),
+ PINCTRL_PIN(277, "FUSA_DIAGTEST_MODE"),
+ PINCTRL_PIN(278, "USB2_OCB_4"),
+ PINCTRL_PIN(279, "USB2_OCB_5"),
+ PINCTRL_PIN(280, "USB2_OCB_6"),
+ PINCTRL_PIN(281, "USB2_OCB_7"),
+ /* JTAG */
+ PINCTRL_PIN(282, "JTAG_TDO"),
+ PINCTRL_PIN(283, "JTAGX"),
+ PINCTRL_PIN(284, "PRDYB"),
+ PINCTRL_PIN(285, "PREQB"),
+ PINCTRL_PIN(286, "JTAG_TDI"),
+ PINCTRL_PIN(287, "JTAG_TMS"),
+ PINCTRL_PIN(288, "JTAG_TCK"),
+ PINCTRL_PIN(289, "DBG_PMODE"),
+ PINCTRL_PIN(290, "CPU_TRSTB"),
+};
+
+static const struct intel_padgroup tglh_community0_gpps[] = {
+ TGL_GPP(0, 0, 24, 0), /* GPP_A */
+ TGL_GPP(1, 25, 44, 128), /* GPP_R */
+ TGL_GPP(2, 45, 70, 32), /* GPP_B */
+ TGL_GPP(3, 71, 78, INTEL_GPIO_BASE_NOMAP), /* vGPIO_0 */
+};
+
+static const struct intel_padgroup tglh_community1_gpps[] = {
+ TGL_GPP(0, 79, 104, 96), /* GPP_D */
+ TGL_GPP(1, 105, 128, 64), /* GPP_C */
+ TGL_GPP(2, 129, 136, 160), /* GPP_S */
+ TGL_GPP(3, 137, 153, 192), /* GPP_G */
+ TGL_GPP(4, 154, 180, 224), /* vGPIO */
+};
+
+static const struct intel_padgroup tglh_community3_gpps[] = {
+ TGL_GPP(0, 181, 193, 256), /* GPP_E */
+ TGL_GPP(1, 194, 217, 288), /* GPP_F */
+};
+
+static const struct intel_padgroup tglh_community4_gpps[] = {
+ TGL_GPP(0, 218, 241, 320), /* GPP_H */
+ TGL_GPP(1, 242, 251, 384), /* GPP_J */
+ TGL_GPP(2, 252, 266, 352), /* GPP_K */
+};
+
+static const struct intel_padgroup tglh_community5_gpps[] = {
+ TGL_GPP(0, 267, 281, 416), /* GPP_I */
+ TGL_GPP(1, 282, 290, INTEL_GPIO_BASE_NOMAP), /* JTAG */
+};
+
+static const struct intel_community tglh_communities[] = {
+ TGL_COMMUNITY(0, 0, 78, tglh_community0_gpps),
+ TGL_COMMUNITY(1, 79, 180, tglh_community1_gpps),
+ TGL_COMMUNITY(2, 181, 217, tglh_community3_gpps),
+ TGL_COMMUNITY(3, 218, 266, tglh_community4_gpps),
+ TGL_COMMUNITY(4, 267, 290, tglh_community5_gpps),
+};
+
+static const struct intel_pinctrl_soc_data tglh_soc_data = {
+ .pins = tglh_pins,
+ .npins = ARRAY_SIZE(tglh_pins),
+ .communities = tglh_communities,
+ .ncommunities = ARRAY_SIZE(tglh_communities),
+};
+
 static const struct acpi_device_id tgl_pinctrl_acpi_match[] = {
  { "INT34C5", (kernel_ulong_t)&tgllp_soc_data },
+ { "INT34C6", (kernel_ulong_t)&tglh_soc_data },
  { }
 };
 MODULE_DEVICE_TABLE(acpi, tgl_pinctrl_acpi_match);
--
2.25.1


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ACK/Cmnt[G]: [PATCH 00/10][SRU][G][OEM-5.6] Intel Tiger Lake-H IDs supplement

Stefan Bader-2
In reply to this post by AceLan Kao
On 18.11.20 07:24, AceLan Kao wrote:

> BugLink: https://bugs.launchpad.net/bugs/1904521
>
> [Impact]
> Intel Tiger Lake-H platform requires new pin settings and IDs to enable.
>
> [Fix]
> Intel provides us a list of TGL-H commits from 5.8 and 5.9, we need all of
> the commits to enable TGL-H platforms completely.
>
> [Test]
> Verified those commits on Intel TGL-H SDP
>
> [Regression potential]
> Low, all of those commits are adding new IDs for TGL-H platform.
>
> Alexander Shishkin (1):
>   intel_th: pci: Add Tiger Lake PCH-H support
>
> Andy Shevchenko (2):
>   mfd: intel-lpss: Add Intel Tiger Lake PCH-H PCI IDs
>   pinctrl: intel: Introduce common flags for GPIO mapping scheme
>
> Boris Brezillon (1):
>   mtd: spi-nor: Prepare core / manufacturer code split
>
> Guenter Roeck (1):
>   mtd: spi-nor: Compile files in controllers/ directory
>
> Heikki Krogerus (1):
>   usb: dwc3: pci: add support for the Intel Tiger Lake PCH -H variant
>
> Jarkko Nikula (2):
>   i2c: i801: Add support for Intel Tiger Lake PCH-H
>   spi: pxa2xx: Add support for Intel Tiger Lake PCH-H
>
> Mika Westerberg (2):
>   mtd: spi-nor: intel-spi: Add support for Intel Tiger Lake-H SPI serial
>     flash
>   pinctrl: tigerlake: Add support for Tiger Lake-H
>
>  drivers/hwtracing/intel_th/pci.c              |   5 +
>  drivers/i2c/busses/i2c-i801.c                 |   4 +
>  drivers/mfd/intel-lpss-pci.c                  |  16 +
>  drivers/mtd/spi-nor/Kconfig                   |  83 +---
>  drivers/mtd/spi-nor/Makefile                  |  12 +-
>  drivers/mtd/spi-nor/controllers/Kconfig       |  83 ++++
>  drivers/mtd/spi-nor/controllers/Makefile      |   9 +
>  .../spi-nor/{ => controllers}/aspeed-smc.c    |   0
>  .../{ => controllers}/cadence-quadspi.c       |   0
>  .../mtd/spi-nor/{ => controllers}/hisi-sfc.c  |   0
>  .../spi-nor/{ => controllers}/intel-spi-pci.c |   1 +
>  .../{ => controllers}/intel-spi-platform.c    |   0
>  .../mtd/spi-nor/{ => controllers}/intel-spi.c |   0
>  .../mtd/spi-nor/{ => controllers}/intel-spi.h |   0
>  .../spi-nor/{ => controllers}/mtk-quadspi.c   |   0
>  .../mtd/spi-nor/{ => controllers}/nxp-spifi.c |   0
>  drivers/mtd/spi-nor/{spi-nor.c => core.c}     |   0
>  drivers/pinctrl/intel/pinctrl-intel.c         |  19 +-
>  drivers/pinctrl/intel/pinctrl-intel.h         |  14 +-
>  drivers/pinctrl/intel/pinctrl-tigerlake.c     | 358 ++++++++++++++++++
>  drivers/spi/spi-pxa2xx.c                      |   5 +
>  drivers/usb/dwc3/dwc3-pci.c                   |   4 +
>  22 files changed, 515 insertions(+), 98 deletions(-)
>  create mode 100644 drivers/mtd/spi-nor/controllers/Kconfig
>  create mode 100644 drivers/mtd/spi-nor/controllers/Makefile
>  rename drivers/mtd/spi-nor/{ => controllers}/aspeed-smc.c (100%)
>  rename drivers/mtd/spi-nor/{ => controllers}/cadence-quadspi.c (100%)
>  rename drivers/mtd/spi-nor/{ => controllers}/hisi-sfc.c (100%)
>  rename drivers/mtd/spi-nor/{ => controllers}/intel-spi-pci.c (97%)
>  rename drivers/mtd/spi-nor/{ => controllers}/intel-spi-platform.c (100%)
>  rename drivers/mtd/spi-nor/{ => controllers}/intel-spi.c (100%)
>  rename drivers/mtd/spi-nor/{ => controllers}/intel-spi.h (100%)
>  rename drivers/mtd/spi-nor/{ => controllers}/mtk-quadspi.c (100%)
>  rename drivers/mtd/spi-nor/{ => controllers}/nxp-spifi.c (100%)
>  rename drivers/mtd/spi-nor/{spi-nor.c => core.c} (100%)
>
I only looked at the Groovy patches and both appear reasonable.

Acked-by: Stefan Bader <[hidden email]>


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ACK[G]/cmnt: [PATCH 00/10][SRU][G][OEM-5.6] Intel Tiger Lake-H IDs supplement

Kleber Souza
In reply to this post by AceLan Kao
On 18.11.20 07:24, AceLan Kao wrote:

> BugLink: https://bugs.launchpad.net/bugs/1904521
>
> [Impact]
> Intel Tiger Lake-H platform requires new pin settings and IDs to enable.
>
> [Fix]
> Intel provides us a list of TGL-H commits from 5.8 and 5.9, we need all of
> the commits to enable TGL-H platforms completely.
>
> [Test]
> Verified those commits on Intel TGL-H SDP
>
> [Regression potential]
> Low, all of those commits are adding new IDs for TGL-H platform.
>
> Alexander Shishkin (1):
>    intel_th: pci: Add Tiger Lake PCH-H support
>
> Andy Shevchenko (2):
>    mfd: intel-lpss: Add Intel Tiger Lake PCH-H PCI IDs
>    pinctrl: intel: Introduce common flags for GPIO mapping scheme
>
> Boris Brezillon (1):
>    mtd: spi-nor: Prepare core / manufacturer code split
>
> Guenter Roeck (1):
>    mtd: spi-nor: Compile files in controllers/ directory
>
> Heikki Krogerus (1):
>    usb: dwc3: pci: add support for the Intel Tiger Lake PCH -H variant
>
> Jarkko Nikula (2):
>    i2c: i801: Add support for Intel Tiger Lake PCH-H
>    spi: pxa2xx: Add support for Intel Tiger Lake PCH-H
>
> Mika Westerberg (2):
>    mtd: spi-nor: intel-spi: Add support for Intel Tiger Lake-H SPI serial
>      flash
>    pinctrl: tigerlake: Add support for Tiger Lake-H
>
>   drivers/hwtracing/intel_th/pci.c              |   5 +
>   drivers/i2c/busses/i2c-i801.c                 |   4 +
>   drivers/mfd/intel-lpss-pci.c                  |  16 +
>   drivers/mtd/spi-nor/Kconfig                   |  83 +---
>   drivers/mtd/spi-nor/Makefile                  |  12 +-
>   drivers/mtd/spi-nor/controllers/Kconfig       |  83 ++++
>   drivers/mtd/spi-nor/controllers/Makefile      |   9 +
>   .../spi-nor/{ => controllers}/aspeed-smc.c    |   0
>   .../{ => controllers}/cadence-quadspi.c       |   0
>   .../mtd/spi-nor/{ => controllers}/hisi-sfc.c  |   0
>   .../spi-nor/{ => controllers}/intel-spi-pci.c |   1 +
>   .../{ => controllers}/intel-spi-platform.c    |   0
>   .../mtd/spi-nor/{ => controllers}/intel-spi.c |   0
>   .../mtd/spi-nor/{ => controllers}/intel-spi.h |   0
>   .../spi-nor/{ => controllers}/mtk-quadspi.c   |   0
>   .../mtd/spi-nor/{ => controllers}/nxp-spifi.c |   0
>   drivers/mtd/spi-nor/{spi-nor.c => core.c}     |   0
>   drivers/pinctrl/intel/pinctrl-intel.c         |  19 +-
>   drivers/pinctrl/intel/pinctrl-intel.h         |  14 +-
>   drivers/pinctrl/intel/pinctrl-tigerlake.c     | 358 ++++++++++++++++++
>   drivers/spi/spi-pxa2xx.c                      |   5 +
>   drivers/usb/dwc3/dwc3-pci.c                   |   4 +
>   22 files changed, 515 insertions(+), 98 deletions(-)
>   create mode 100644 drivers/mtd/spi-nor/controllers/Kconfig
>   create mode 100644 drivers/mtd/spi-nor/controllers/Makefile
>   rename drivers/mtd/spi-nor/{ => controllers}/aspeed-smc.c (100%)
>   rename drivers/mtd/spi-nor/{ => controllers}/cadence-quadspi.c (100%)
>   rename drivers/mtd/spi-nor/{ => controllers}/hisi-sfc.c (100%)
>   rename drivers/mtd/spi-nor/{ => controllers}/intel-spi-pci.c (97%)
>   rename drivers/mtd/spi-nor/{ => controllers}/intel-spi-platform.c (100%)
>   rename drivers/mtd/spi-nor/{ => controllers}/intel-spi.c (100%)
>   rename drivers/mtd/spi-nor/{ => controllers}/intel-spi.h (100%)
>   rename drivers/mtd/spi-nor/{ => controllers}/mtk-quadspi.c (100%)
>   rename drivers/mtd/spi-nor/{ => controllers}/nxp-spifi.c (100%)
>   rename drivers/mtd/spi-nor/{spi-nor.c => core.c} (100%)
>

I have reviewed only the patches for Groovy, they seem straightforward
adding support for new hw.

Acked-by: Kleber Sacilotto de Souza <[hidden email]>

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APPLIED: [PATCH 1/2][SRU][Groovy] Intel Tiger Lake-H IDs supplement

William Breathitt Gray
In reply to this post by AceLan Kao
On Wed, Nov 18, 2020 at 02:24:39PM +0800, AceLan Kao wrote:

> BugLink: https://bugs.launchpad.net/bugs/1904521
>
> [Impact]
> Intel Tiger Lake-H platform requires new pin settings and IDs to enable.
>
> [Fix]
> Intel provides us a list of TGL-H commits from 5.8 and 5.9, we need all of
> the commits to enable TGL-H platforms completely.
>
> [Test]
> Verified those commits on Intel TGL-H SDP
>
> [Regression potential]
> Low, all of those commits are adding new IDs for TGL-H platform.
>
> Alexander Shishkin (1):
>   intel_th: pci: Add Tiger Lake PCH-H support
>
> Andy Shevchenko (2):
>   mfd: intel-lpss: Add Intel Tiger Lake PCH-H PCI IDs
>   pinctrl: intel: Introduce common flags for GPIO mapping scheme
>
> Boris Brezillon (1):
>   mtd: spi-nor: Prepare core / manufacturer code split
>
> Guenter Roeck (1):
>   mtd: spi-nor: Compile files in controllers/ directory
>
> Heikki Krogerus (1):
>   usb: dwc3: pci: add support for the Intel Tiger Lake PCH -H variant
>
> Jarkko Nikula (2):
>   i2c: i801: Add support for Intel Tiger Lake PCH-H
>   spi: pxa2xx: Add support for Intel Tiger Lake PCH-H
>
> Mika Westerberg (2):
>   mtd: spi-nor: intel-spi: Add support for Intel Tiger Lake-H SPI serial
>     flash
>   pinctrl: tigerlake: Add support for Tiger Lake-H
>
>  drivers/hwtracing/intel_th/pci.c              |   5 +
>  drivers/i2c/busses/i2c-i801.c                 |   4 +
>  drivers/mfd/intel-lpss-pci.c                  |  16 +
>  drivers/mtd/spi-nor/Kconfig                   |  83 +---
>  drivers/mtd/spi-nor/Makefile                  |  12 +-
>  drivers/mtd/spi-nor/controllers/Kconfig       |  83 ++++
>  drivers/mtd/spi-nor/controllers/Makefile      |   9 +
>  .../spi-nor/{ => controllers}/aspeed-smc.c    |   0
>  .../{ => controllers}/cadence-quadspi.c       |   0
>  .../mtd/spi-nor/{ => controllers}/hisi-sfc.c  |   0
>  .../spi-nor/{ => controllers}/intel-spi-pci.c |   1 +
>  .../{ => controllers}/intel-spi-platform.c    |   0
>  .../mtd/spi-nor/{ => controllers}/intel-spi.c |   0
>  .../mtd/spi-nor/{ => controllers}/intel-spi.h |   0
>  .../spi-nor/{ => controllers}/mtk-quadspi.c   |   0
>  .../mtd/spi-nor/{ => controllers}/nxp-spifi.c |   0
>  drivers/mtd/spi-nor/{spi-nor.c => core.c}     |   0
>  drivers/pinctrl/intel/pinctrl-intel.c         |  19 +-
>  drivers/pinctrl/intel/pinctrl-intel.h         |  14 +-
>  drivers/pinctrl/intel/pinctrl-tigerlake.c     | 358 ++++++++++++++++++
>  drivers/spi/spi-pxa2xx.c                      |   5 +
>  drivers/usb/dwc3/dwc3-pci.c                   |   4 +
>  22 files changed, 515 insertions(+), 98 deletions(-)
>  create mode 100644 drivers/mtd/spi-nor/controllers/Kconfig
>  create mode 100644 drivers/mtd/spi-nor/controllers/Makefile
>  rename drivers/mtd/spi-nor/{ => controllers}/aspeed-smc.c (100%)
>  rename drivers/mtd/spi-nor/{ => controllers}/cadence-quadspi.c (100%)
>  rename drivers/mtd/spi-nor/{ => controllers}/hisi-sfc.c (100%)
>  rename drivers/mtd/spi-nor/{ => controllers}/intel-spi-pci.c (97%)
>  rename drivers/mtd/spi-nor/{ => controllers}/intel-spi-platform.c (100%)
>  rename drivers/mtd/spi-nor/{ => controllers}/intel-spi.c (100%)
>  rename drivers/mtd/spi-nor/{ => controllers}/intel-spi.h (100%)
>  rename drivers/mtd/spi-nor/{ => controllers}/mtk-quadspi.c (100%)
>  rename drivers/mtd/spi-nor/{ => controllers}/nxp-spifi.c (100%)
>  rename drivers/mtd/spi-nor/{spi-nor.c => core.c} (100%)
>
> --
> 2.25.1
Applied to Groovy:linux.

William Breathitt Gray

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