[PATCH 00/10][SRU][OEM-5.10][Unstable] Support CML-S CPU + TGP PCH

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[PATCH 00/10][SRU][OEM-5.10][Unstable] Support CML-S CPU + TGP PCH

AceLan Kao
From: "Chia-Lin Kao (AceLan)" <[hidden email]>

https://bugs.launchpad.net/bugs/1909457

[Impact]
i915 driver gives below warnings that CML-S GPU doesn't work with TGL/RKL
PCH, and the screen is blank.

kernel: i915 0000:00:02.0: drm_WARN_ON(!IS_PLATFORM(dev_priv, INTEL_TIGERLAKE) && !IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE))

[Fix]
Intel provides us a new patch for this issue
https://patchwork.freedesktop.org/patch/412664/

[Test]
Verified on new Dell platforms.

[Where problems could occur]
The first commit reverts the patch that didn't find its way to upstream.
The second to forth commits are to enable DG1 which applied for solving conflicts.
The fifth and sixth commit splits code for EHL and JSL.
The seventh and eighth commits rename enums, no function changes.
The ninth commit is the newer version of the first reverted commit.
The tenth commit adds CML CPU support on TGP PCH which fixes this issue.
According to the above explanation,
1. the DG1 in newly enabled by commits 2 to 4, no regression could occur,
2. the EHL and JSL commits are pretty simple and straightforward, should be safe to include,
3. the first commit is equivalence to the ninth commit
4. the tenth commit is pretty simple to add GEN9 into flow control,
so I think there should be no problems could occur from this patchset.

Chia-Lin Kao (AceLan) (1):
  Revert "UBUNTU: SAUCE: drm/i915/rkl: new rkl ddc map for different
    PCH"

José Roberto de Souza (1):
  drm/i915/display/ehl: Limit eDP to HBR2

Lee Shawn C (1):
  drm/i915/rkl: new rkl ddc map for different PCH

Lucas De Marchi (2):
  drm/i915/dg1: gmbus pin mapping
  drm/i915/dg1: add hpd interrupt handling

Matt Roper (1):
  drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D

Tejas Upadhyay (2):
  drm/i915/jsl: Split EHL/JSL platform info and PCI ids
  UBUNTU: SAUCE: drm/i915/gen9_bc : Add TGP PCH support

Ville Syrjälä (2):
  drm/i915: Add PORT_TCn aliases to enum port
  drm/i915: s/PORT_TC/TC_PORT_/

 drivers/gpu/drm/i915/display/icl_dsi.c        |   4 +-
 drivers/gpu/drm/i915/display/intel_bios.c     |  35 +++---
 drivers/gpu/drm/i915/display/intel_cdclk.c    |   4 +-
 .../gpu/drm/i915/display/intel_combo_phy.c    |   9 +-
 drivers/gpu/drm/i915/display/intel_ddi.c      |  47 ++++---
 drivers/gpu/drm/i915/display/intel_display.c  |  47 ++++---
 drivers/gpu/drm/i915/display/intel_display.h  |  24 ++--
 drivers/gpu/drm/i915/display/intel_dp.c       |  11 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c |  16 +--
 drivers/gpu/drm/i915/display/intel_gmbus.c    |  15 ++-
 drivers/gpu/drm/i915/display/intel_hdmi.c     |  29 ++++-
 drivers/gpu/drm/i915/display/intel_tc.c       |   2 +-
 drivers/gpu/drm/i915/gt/intel_sseu.c          |   2 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c   |   4 +-
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c      |   1 +
 drivers/gpu/drm/i915/i915_drv.h               |   7 +-
 drivers/gpu/drm/i915/i915_irq.c               | 115 +++++++++++-------
 drivers/gpu/drm/i915/i915_pci.c               |   9 ++
 drivers/gpu/drm/i915/i915_reg.h               |  68 ++++++-----
 drivers/gpu/drm/i915/intel_device_info.c      |   1 +
 drivers/gpu/drm/i915/intel_device_info.h      |   1 +
 drivers/gpu/drm/i915/intel_pch.c              |   9 +-
 include/drm/i915_pciids.h                     |   9 +-
 23 files changed, 299 insertions(+), 170 deletions(-)

--
2.25.1


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[PATCH 01/10][SRU][OEM-5.10] Revert "UBUNTU: SAUCE: drm/i915/rkl: new rkl ddc map for different PCH"

AceLan Kao
From: "Chia-Lin Kao (AceLan)" <[hidden email]>

BugLink: https://bugs.launchpad.net/bugs/1909457

This reverts commit 0d2ccb7f5e6cada60453a8273f5d9e74b0b4d868.

Signed-off-by: Chia-Lin Kao (AceLan) <[hidden email]>
---
 drivers/gpu/drm/i915/display/intel_bios.c     | 16 ++--------------
 drivers/gpu/drm/i915/display/intel_vbt_defs.h |  2 --
 2 files changed, 2 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 23614a6728f1..390ebff0f1a3 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1598,26 +1598,14 @@ static const u8 icp_ddc_pin_map[] = {
  [TGL_DDC_BUS_PORT_6] = GMBUS_PIN_14_TC6_TGP,
 };
 
-static const u8 rkl_pch_tgp_ddc_pin_map[] = {
- [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT,
- [ICL_DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT,
- [RKL_DDC_BUS_DDI_D] = GMBUS_PIN_9_TC1_ICP,
- [RKL_DDC_BUS_DDI_E] = GMBUS_PIN_10_TC2_ICP,
-};
-
 static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
 {
  const u8 *ddc_pin_map;
  int n_entries;
 
  if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) {
- if (IS_ROCKETLAKE(dev_priv)) {
- ddc_pin_map = rkl_pch_tgp_ddc_pin_map;
- n_entries = ARRAY_SIZE(rkl_pch_tgp_ddc_pin_map);
- } else {
- ddc_pin_map = icp_ddc_pin_map;
- n_entries = ARRAY_SIZE(icp_ddc_pin_map);
- }
+ ddc_pin_map = icp_ddc_pin_map;
+ n_entries = ARRAY_SIZE(icp_ddc_pin_map);
  } else if (HAS_PCH_CNP(dev_priv)) {
  ddc_pin_map = cnp_ddc_pin_map;
  n_entries = ARRAY_SIZE(cnp_ddc_pin_map);
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 1a17ef519d74..54bcc6a6947c 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -319,8 +319,6 @@ enum vbt_gmbus_ddi {
  ICL_DDC_BUS_DDI_A = 0x1,
  ICL_DDC_BUS_DDI_B,
  TGL_DDC_BUS_DDI_C,
- RKL_DDC_BUS_DDI_D = 0x3,
- RKL_DDC_BUS_DDI_E,
  ICL_DDC_BUS_PORT_1 = 0x4,
  ICL_DDC_BUS_PORT_2,
  ICL_DDC_BUS_PORT_3,
--
2.25.1


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[PATCH 02/10][SRU][OEM-5.10] drm/i915/dg1: gmbus pin mapping

AceLan Kao
In reply to this post by AceLan Kao
From: Lucas De Marchi <[hidden email]>

BugLink: https://bugs.launchpad.net/bugs/1909457

Add tables to map the GMBUS pin pairs to GPIO registers and port to DDC.
From spec we have registers GPIO_CTL[1-4], so we should not do the 4->9
mapping as in ICL/TGL.

The values for VBT seem wrong in BSpec. For the current boards we
actually have a 1:1 mapping.

BSpec: 49311, 49945, 20124

Cc: Aditya Swarup <[hidden email]>
Cc: Matt Roper <[hidden email]>
Signed-off-by: Lucas De Marchi <[hidden email]>
Reviewed-by: Matt Roper <[hidden email]>
Link: https://patchwork.freedesktop.org/patch/msgid/20201007002210.3678024-5-lucas.demarchi@...
(cherry picked from commit fb7318c37afac6c6c7d18f893b3df962388cf763)
Signed-off-by: Chia-Lin Kao (AceLan) <[hidden email]>
---
 drivers/gpu/drm/i915/display/intel_bios.c  |  4 +++-
 drivers/gpu/drm/i915/display/intel_gmbus.c | 15 +++++++++++++--
 drivers/gpu/drm/i915/display/intel_hdmi.c  |  9 ++++++++-
 3 files changed, 24 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 390ebff0f1a3..74679ccf99fc 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1603,7 +1603,9 @@ static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
  const u8 *ddc_pin_map;
  int n_entries;
 
- if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) {
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) {
+ return vbt_pin;
+ } else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) {
  ddc_pin_map = icp_ddc_pin_map;
  n_entries = ARRAY_SIZE(icp_ddc_pin_map);
  } else if (HAS_PCH_CNP(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
index e6b8d6dfb598..b0d71bbbf2ad 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -90,11 +90,20 @@ static const struct gmbus_pin gmbus_pins_icp[] = {
  [GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO },
 };
 
+static const struct gmbus_pin gmbus_pins_dg1[] = {
+ [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
+ [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
+ [GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
+ [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
+};
+
 /* pin is expected to be valid */
 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
      unsigned int pin)
 {
- if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+ return &gmbus_pins_dg1[pin];
+ else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
  return &gmbus_pins_icp[pin];
  else if (HAS_PCH_CNP(dev_priv))
  return &gmbus_pins_cnp[pin];
@@ -113,7 +122,9 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
 {
  unsigned int size;
 
- if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+ size = ARRAY_SIZE(gmbus_pins_dg1);
+ else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
  size = ARRAY_SIZE(gmbus_pins_icp);
  else if (HAS_PCH_CNP(dev_priv))
  size = ARRAY_SIZE(gmbus_pins_cnp);
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 05a8a1d58bad..866bc6b4b73c 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -3145,6 +3145,11 @@ static u8 rkl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
  return GMBUS_PIN_1_BXT + phy;
 }
 
+static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
+{
+ return intel_port_to_phy(dev_priv, port) + 1;
+}
+
 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
       enum port port)
 {
@@ -3182,7 +3187,9 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
  return ddc_pin;
  }
 
- if (IS_ROCKETLAKE(dev_priv))
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+ ddc_pin = dg1_port_to_ddc_pin(dev_priv, port);
+ else if (IS_ROCKETLAKE(dev_priv))
  ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
  else if (HAS_PCH_MCC(dev_priv))
  ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
--
2.25.1


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[PATCH 03/10][SRU][OEM-5.10] drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D

AceLan Kao
In reply to this post by AceLan Kao
From: Matt Roper <[hidden email]>

BugLink: https://bugs.launchpad.net/bugs/1909457

The only bit we use in PHY_MISC is DE_IO_COMP_PWR_DOWN, and the bspec
details for that bit tell us that it need only be set for PHY-A and
PHY-B.  It also turns out that there isn't even an instance of the
PHY_MISC register for PHY-D on this platform.  Let's extend the EHL/RKL
logic that conditionally skips PHY_MISC usage to DG1 as well.

Bspec: 50107
Cc: Aditya Swarup <[hidden email]>
Cc: Clinton Taylor <[hidden email]>
Signed-off-by: Matt Roper <[hidden email]>
Signed-off-by: Lucas De Marchi <[hidden email]>
Reviewed-by: Anusha Srivatsa <[hidden email]>
Link: https://patchwork.freedesktop.org/patch/msgid/20201007002210.3678024-6-lucas.demarchi@...
(cherry picked from commit 0642c2b837495b6c6b60349c0e4e1b4fe2bedc0a)
Signed-off-by: Chia-Lin Kao (AceLan) <[hidden email]>
---
 drivers/gpu/drm/i915/display/intel_combo_phy.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index 157d8c8c605a..07c9fa2fb835 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -189,7 +189,8 @@ static bool has_phy_misc(struct drm_i915_private *i915, enum phy phy)
  * other combo PHY's.
  */
  if (IS_ELKHARTLAKE(i915) ||
-    IS_ROCKETLAKE(i915))
+    IS_ROCKETLAKE(i915) ||
+    IS_DG1(i915))
  return phy < PHY_C;
 
  return true;
--
2.25.1


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[PATCH 04/10][SRU][OEM-5.10] drm/i915/dg1: add hpd interrupt handling

AceLan Kao
In reply to this post by AceLan Kao
From: Lucas De Marchi <[hidden email]>

BugLink: https://bugs.launchpad.net/bugs/1909457

DG1 has one more combo phy port, no TC and all irq handling goes through
SDE, like for MCC.

v2: Also change intel_hpd_pin_default() to include DG1 mapping
v3, v4: Rebase on hpd refactor

Cc: Ville Syrjälä <[hidden email]>
Cc: Anshuman Gupta <[hidden email]>
Cc: José Roberto de Souza <[hidden email]>
Cc: Imre Deak <[hidden email]>
Signed-off-by: Lucas De Marchi <[hidden email]>
Reviewed-by: Matt Roper <[hidden email]>
Link: https://patchwork.freedesktop.org/patch/msgid/20201021082034.3170478-2-lucas.demarchi@...
(cherry picked from commit 229f31e2d370d36c2345dadb821c856f61d13197)
Signed-off-by: Chia-Lin Kao (AceLan) <[hidden email]>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 13 ++++++++-
 drivers/gpu/drm/i915/i915_irq.c          | 37 ++++++++++++++++++++----
 drivers/gpu/drm/i915/i915_reg.h          |  8 +++++
 3 files changed, 51 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index e19cbb43e028..119634fbb52c 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -5064,6 +5064,15 @@ static bool hti_uses_phy(struct drm_i915_private *i915, enum phy phy)
  i915->hti_state & HDPORT_PHY_USED_HDMI(phy));
 }
 
+static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv,
+ enum port port)
+{
+ if (port >= PORT_D)
+ return HPD_PORT_C + port - PORT_D;
+ else
+ return HPD_PORT_A + port - PORT_A;
+}
+
 static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv,
  enum port port)
 {
@@ -5193,7 +5202,9 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
  encoder->cloneable = 0;
  encoder->pipe_mask = ~0;
 
- if (IS_ROCKETLAKE(dev_priv))
+ if (IS_DG1(dev_priv))
+ encoder->hpd_pin = dg1_hpd_pin(dev_priv, port);
+ else if (IS_ROCKETLAKE(dev_priv))
  encoder->hpd_pin = rkl_hpd_pin(dev_priv, port);
  else if (INTEL_GEN(dev_priv) >= 12)
  encoder->hpd_pin = tgl_hpd_pin(dev_priv, port);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 759f523c6a6b..4676ee791950 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -152,6 +152,13 @@ static const u32 hpd_icp[HPD_NUM_PINS] = {
  [HPD_PORT_TC6] = SDE_TC_HOTPLUG_ICP(PORT_TC6),
 };
 
+static const u32 hpd_sde_dg1[HPD_NUM_PINS] = {
+ [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PORT_A),
+ [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PORT_B),
+ [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(PORT_C),
+ [HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(PORT_D),
+};
+
 static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
 {
  struct i915_hotplug *hpd = &dev_priv->hotplug;
@@ -176,11 +183,14 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
  else
  hpd->hpd = hpd_ilk;
 
- if (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv))
+ if ((INTEL_PCH_TYPE(dev_priv) < PCH_DG1) &&
+    (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv)))
  return;
 
- if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv) ||
-    HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv))
+ if (HAS_PCH_DG1(dev_priv))
+ hpd->pch_hpd = hpd_sde_dg1;
+ else if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv) ||
+ HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv))
  hpd->pch_hpd = hpd_icp;
  else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_SPT(dev_priv))
  hpd->pch_hpd = hpd_spt;
@@ -1070,6 +1080,8 @@ static bool icp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
  return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_B);
  case HPD_PORT_C:
  return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_C);
+ case HPD_PORT_D:
+ return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_D);
  default:
  return false;
  }
@@ -1843,7 +1855,10 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
  u32 ddi_hotplug_trigger, tc_hotplug_trigger;
  u32 pin_mask = 0, long_mask = 0;
 
- if (HAS_PCH_TGP(dev_priv)) {
+ if (HAS_PCH_DG1(dev_priv)) {
+ ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_DG1;
+ tc_hotplug_trigger = 0;
+ } else if (HAS_PCH_TGP(dev_priv)) {
  ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
  tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP;
  } else if (HAS_PCH_JSP(dev_priv)) {
@@ -3095,6 +3110,12 @@ static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv)
   TGP_DDI_HPD_ENABLE_MASK, 0);
 }
 
+static void dg1_hpd_irq_setup(struct drm_i915_private *dev_priv)
+{
+ icp_hpd_irq_setup(dev_priv,
+  DG1_DDI_HPD_ENABLE_MASK, 0);
+}
+
 static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
 {
  u32 hotplug;
@@ -3478,7 +3499,9 @@ static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
  gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
  I915_WRITE(SDEIMR, ~mask);
 
- if (HAS_PCH_TGP(dev_priv)) {
+ if (HAS_PCH_DG1(dev_priv))
+ icp_ddi_hpd_detection_setup(dev_priv, DG1_DDI_HPD_ENABLE_MASK);
+ else if (HAS_PCH_TGP(dev_priv)) {
  icp_ddi_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK);
  icp_tc_hpd_detection_setup(dev_priv, TGP_TC_HPD_ENABLE_MASK);
  } else if (HAS_PCH_JSP(dev_priv)) {
@@ -3995,7 +4018,9 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
  if (I915_HAS_HOTPLUG(dev_priv))
  dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
  } else {
- if (HAS_PCH_JSP(dev_priv))
+ if (HAS_PCH_DG1(dev_priv))
+ dev_priv->display.hpd_irq_setup = dg1_hpd_irq_setup;
+ else if (HAS_PCH_JSP(dev_priv))
  dev_priv->display.hpd_irq_setup = jsp_hpd_irq_setup;
  else if (HAS_PCH_MCC(dev_priv))
  dev_priv->display.hpd_irq_setup = mcc_hpd_irq_setup;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5287433f028b..fef108d7e22e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8227,6 +8227,10 @@ enum {
  SDE_TC_HOTPLUG_ICP(PORT_TC3) | \
  SDE_TC_HOTPLUG_ICP(PORT_TC2) | \
  SDE_TC_HOTPLUG_ICP(PORT_TC1))
+#define SDE_DDI_MASK_DG1 (SDE_DDI_HOTPLUG_ICP(PORT_D) | \
+ SDE_DDI_HOTPLUG_ICP(PORT_C) | \
+ SDE_DDI_HOTPLUG_ICP(PORT_B) | \
+ SDE_DDI_HOTPLUG_ICP(PORT_A))
 
 #define SDEISR  _MMIO(0xc4000)
 #define SDEIMR  _MMIO(0xc4004)
@@ -8426,6 +8430,10 @@ enum {
 #define TGP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(PORT_TC6) | \
  ICP_TC_HPD_ENABLE(PORT_TC5) | \
  ICP_TC_HPD_ENABLE_MASK)
+#define DG1_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_D) | \
+ SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_C) | \
+ SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \
+ SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A))
 
 #define _PCH_DPLL_A              0xc6014
 #define _PCH_DPLL_B              0xc6018
--
2.25.1


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[PATCH 05/10][SRU][OEM-5.10] drm/i915/display/ehl: Limit eDP to HBR2

AceLan Kao
In reply to this post by AceLan Kao
From: José Roberto de Souza <[hidden email]>

BugLink: https://bugs.launchpad.net/bugs/1909457

Recent update in documentation defeatured eDP HBR3 for EHL and JSL.

v2:
- Remove dead code in ehl_get_combo_buf_trans()

v3:
- Rebase

BSpec: 32247
Cc: Matt Roper <[hidden email]>
Cc: Vidya Srinivas <[hidden email]>
Reviewed-by: Matt Roper <[hidden email]>
Signed-off-by: José Roberto de Souza <[hidden email]>
Link: https://patchwork.freedesktop.org/patch/msgid/20201005175447.93430-1-jose.souza@...
(cherry picked from commit cf72562094a0930ea158ca6e7c4eab9c71deab2a)
Signed-off-by: Chia-Lin Kao (AceLan) <[hidden email]>
---
 drivers/gpu/drm/i915/display/intel_ddi.c |  9 ++-------
 drivers/gpu/drm/i915/display/intel_dp.c  | 11 ++++++++++-
 2 files changed, 12 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 119634fbb52c..f70cb3fe6d11 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1142,13 +1142,8 @@ ehl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
  struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 
  if (dev_priv->vbt.edp.low_vswing) {
- if (crtc_state->port_clock > 540000) {
- *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
- return icl_combo_phy_ddi_translations_edp_hbr3;
- } else {
- *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
- return icl_combo_phy_ddi_translations_edp_hbr2;
- }
+ *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
+ return icl_combo_phy_ddi_translations_edp_hbr2;
  }
 
  return ehl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 49b3cf181c74..7a15f923b831 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -285,13 +285,20 @@ static int icl_max_source_rate(struct intel_dp *intel_dp)
  enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
 
  if (intel_phy_is_combo(dev_priv, phy) &&
-    !IS_ELKHARTLAKE(dev_priv) &&
     !intel_dp_is_edp(intel_dp))
  return 540000;
 
  return 810000;
 }
 
+static int ehl_max_source_rate(struct intel_dp *intel_dp)
+{
+ if (intel_dp_is_edp(intel_dp))
+ return 540000;
+
+ return 810000;
+}
+
 static void
 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 {
@@ -326,6 +333,8 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
  size = ARRAY_SIZE(cnl_rates);
  if (IS_GEN(dev_priv, 10))
  max_rate = cnl_max_source_rate(intel_dp);
+ else if (IS_ELKHARTLAKE(dev_priv))
+ max_rate = ehl_max_source_rate(intel_dp);
  else
  max_rate = icl_max_source_rate(intel_dp);
  } else if (IS_GEN9_LP(dev_priv)) {
--
2.25.1


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[PATCH 06/10][SRU][OEM-5.10] drm/i915/jsl: Split EHL/JSL platform info and PCI ids

AceLan Kao
In reply to this post by AceLan Kao
From: Tejas Upadhyay <[hidden email]>

BugLink: https://bugs.launchpad.net/bugs/1909457

Recently we came across requirement to identify EHL and JSL
platform to program them differently. Thus Split the basic
platform definition, macros, and PCI IDs to differentiate
between EHL and JSL platforms. Also, IS_ELKHARTLAKE is replaced
with IS_JSL_EHL everywhere.

Changes since V1 :
        - Rebased to avoid merge conflicts
        - Added missed check for jasperlake in intel_uc_fw.c

Cc : Matt Roper <[hidden email]>
Cc : Ville Syrjälä <[hidden email]>
Signed-off-by: Tejas Upadhyay <[hidden email]>
Reviewed-by: Matt Roper <[hidden email]>
Signed-off-by: Maarten Lankhorst <[hidden email]>
Link: https://patchwork.freedesktop.org/patch/msgid/20201013192948.63470-1-tejaskumarx.surendrakumar.upadhyay@...
(cherry picked from commit 24ea098b7c0d80b56d62a200608e0b029056baf6)
Signed-off-by: Chia-Lin Kao (AceLan) <[hidden email]>
---
 drivers/gpu/drm/i915/display/icl_dsi.c         |  4 ++--
 drivers/gpu/drm/i915/display/intel_cdclk.c     |  4 ++--
 drivers/gpu/drm/i915/display/intel_combo_phy.c |  6 +++---
 drivers/gpu/drm/i915/display/intel_ddi.c       | 12 ++++++------
 drivers/gpu/drm/i915/display/intel_display.c   |  8 ++++----
 drivers/gpu/drm/i915/display/intel_dp.c        |  2 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c  | 16 ++++++++--------
 drivers/gpu/drm/i915/gt/intel_sseu.c           |  2 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c    |  4 ++--
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c       |  1 +
 drivers/gpu/drm/i915/i915_drv.h                |  7 ++++---
 drivers/gpu/drm/i915/i915_pci.c                |  9 +++++++++
 drivers/gpu/drm/i915/intel_device_info.c       |  1 +
 drivers/gpu/drm/i915/intel_device_info.h       |  1 +
 drivers/gpu/drm/i915/intel_pch.c               |  6 +++---
 include/drm/i915_pciids.h                      |  9 ++++++---
 16 files changed, 54 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 68d6c204fc01..ebc83ef78629 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -429,7 +429,7 @@ static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
  intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp);
 
  /* For EHL, TGL, set latency optimization for PCS_DW1 lanes */
- if (IS_ELKHARTLAKE(dev_priv) || (INTEL_GEN(dev_priv) >= 12)) {
+ if (IS_JSL_EHL(dev_priv) || (INTEL_GEN(dev_priv) >= 12)) {
  tmp = intel_de_read(dev_priv,
     ICL_PORT_PCS_DW1_AUX(phy));
  tmp &= ~LATENCY_OPTIM_MASK;
@@ -586,7 +586,7 @@ gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder,
  }
  }
 
- if (IS_ELKHARTLAKE(dev_priv)) {
+ if (IS_JSL_EHL(dev_priv)) {
  for_each_dsi_phy(phy, intel_dsi->phys) {
  tmp = intel_de_read(dev_priv, ICL_DPHY_CHKN(phy));
  tmp |= ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP;
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index cb93f6cf6d37..c6e87569b3d6 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2588,7 +2588,7 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
  */
 void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
 {
- if (IS_ELKHARTLAKE(dev_priv)) {
+ if (IS_JSL_EHL(dev_priv)) {
  if (dev_priv->cdclk.hw.ref == 24000)
  dev_priv->max_cdclk_freq = 552000;
  else
@@ -2815,7 +2815,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
  dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
  dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
  dev_priv->cdclk.table = icl_cdclk_table;
- } else if (IS_ELKHARTLAKE(dev_priv)) {
+ } else if (IS_JSL_EHL(dev_priv)) {
  dev_priv->display.set_cdclk = bxt_set_cdclk;
  dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
  dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index 07c9fa2fb835..66483025c515 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -188,7 +188,7 @@ static bool has_phy_misc(struct drm_i915_private *i915, enum phy phy)
  * PHY-B and may not even have instances of the register for the
  * other combo PHY's.
  */
- if (IS_ELKHARTLAKE(i915) ||
+ if (IS_JSL_EHL(i915) ||
     IS_ROCKETLAKE(i915) ||
     IS_DG1(i915))
  return phy < PHY_C;
@@ -283,7 +283,7 @@ static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
  ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy),
      IREFGEN, IREFGEN);
 
- if (IS_ELKHARTLAKE(dev_priv)) {
+ if (IS_JSL_EHL(dev_priv)) {
  if (ehl_vbt_ddi_d_present(dev_priv))
  expected_val = ICL_PHY_MISC_MUX_DDID;
 
@@ -377,7 +377,7 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
  * "internal" child devices.
  */
  val = intel_de_read(dev_priv, ICL_PHY_MISC(phy));
- if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_A) {
+ if (IS_JSL_EHL(dev_priv) && phy == PHY_A) {
  val &= ~ICL_PHY_MISC_MUX_DDID;
 
  if (ehl_vbt_ddi_d_present(dev_priv))
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index f70cb3fe6d11..4f5607a2bcfe 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2363,7 +2363,7 @@ static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp,
  else
  tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries);
  } else if (INTEL_GEN(dev_priv) == 11) {
- if (IS_ELKHARTLAKE(dev_priv))
+ if (IS_JSL_EHL(dev_priv))
  ehl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
  else if (intel_phy_is_combo(dev_priv, phy))
  icl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
@@ -2544,7 +2544,7 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
 
  if (INTEL_GEN(dev_priv) >= 12)
  ddi_translations = tgl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
- else if (IS_ELKHARTLAKE(dev_priv))
+ else if (IS_JSL_EHL(dev_priv))
  ddi_translations = ehl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
  else
  ddi_translations = icl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
@@ -3135,7 +3135,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
  if (!intel_phy_is_combo(dev_priv, phy))
  intel_de_write(dev_priv, DDI_CLK_SEL(port),
        icl_pll_to_ddi_clk_sel(encoder, crtc_state));
- else if (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C)
+ else if (IS_JSL_EHL(dev_priv) && port >= PORT_C)
  /*
  * MG does not exist but the programming is required
  * to ungate DDIC and DDID
@@ -3184,7 +3184,7 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder)
 
  if (INTEL_GEN(dev_priv) >= 11) {
  if (!intel_phy_is_combo(dev_priv, phy) ||
-    (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C))
+    (IS_JSL_EHL(dev_priv) && port >= PORT_C))
  intel_de_write(dev_priv, DDI_CLK_SEL(port),
        DDI_CLK_SEL_NONE);
  } else if (IS_CANNONLAKE(dev_priv)) {
@@ -4300,7 +4300,7 @@ void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
 {
  if (INTEL_GEN(dev_priv) >= 12 && crtc_state->port_clock > 594000)
  crtc_state->min_voltage_level = 2;
- else if (IS_ELKHARTLAKE(dev_priv) && crtc_state->port_clock > 594000)
+ else if (IS_JSL_EHL(dev_priv) && crtc_state->port_clock > 594000)
  crtc_state->min_voltage_level = 3;
  else if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000)
  crtc_state->min_voltage_level = 1;
@@ -5203,7 +5203,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
  encoder->hpd_pin = rkl_hpd_pin(dev_priv, port);
  else if (INTEL_GEN(dev_priv) >= 12)
  encoder->hpd_pin = tgl_hpd_pin(dev_priv, port);
- else if (IS_ELKHARTLAKE(dev_priv))
+ else if (IS_JSL_EHL(dev_priv))
  encoder->hpd_pin = ehl_hpd_pin(dev_priv, port);
  else if (IS_GEN(dev_priv, 11))
  encoder->hpd_pin = icl_hpd_pin(dev_priv, port);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 7f39b3941785..c1b90c1e590d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7275,7 +7275,7 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
  return false;
  else if (IS_ROCKETLAKE(dev_priv))
  return phy <= PHY_D;
- else if (IS_ELKHARTLAKE(dev_priv))
+ else if (IS_JSL_EHL(dev_priv))
  return phy <= PHY_C;
  else if (INTEL_GEN(dev_priv) >= 11)
  return phy <= PHY_B;
@@ -7289,7 +7289,7 @@ bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
  return false;
  else if (INTEL_GEN(dev_priv) >= 12)
  return phy >= PHY_D && phy <= PHY_I;
- else if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
+ else if (INTEL_GEN(dev_priv) >= 11 && !IS_JSL_EHL(dev_priv))
  return phy >= PHY_C && phy <= PHY_F;
  else
  return false;
@@ -7299,7 +7299,7 @@ enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
 {
  if (IS_ROCKETLAKE(i915) && port >= PORT_D)
  return (enum phy)port - 1;
- else if (IS_ELKHARTLAKE(i915) && port == PORT_D)
+ else if (IS_JSL_EHL(i915) && port == PORT_D)
  return PHY_A;
 
  return (enum phy)port;
@@ -16907,7 +16907,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
  intel_ddi_init(dev_priv, PORT_H);
  intel_ddi_init(dev_priv, PORT_I);
  icl_dsi_init(dev_priv);
- } else if (IS_ELKHARTLAKE(dev_priv)) {
+ } else if (IS_JSL_EHL(dev_priv)) {
  intel_ddi_init(dev_priv, PORT_A);
  intel_ddi_init(dev_priv, PORT_B);
  intel_ddi_init(dev_priv, PORT_C);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 7a15f923b831..18c12ec1738a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -333,7 +333,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
  size = ARRAY_SIZE(cnl_rates);
  if (IS_GEN(dev_priv, 10))
  max_rate = cnl_max_source_rate(intel_dp);
- else if (IS_ELKHARTLAKE(dev_priv))
+ else if (IS_JSL_EHL(dev_priv))
  max_rate = ehl_max_source_rate(intel_dp);
  else
  max_rate = icl_max_source_rate(intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 2cc0e84e41ea..48c30c50a301 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -152,7 +152,7 @@ intel_combo_pll_enable_reg(struct drm_i915_private *i915,
    struct intel_shared_dpll *pll)
 {
 
- if (IS_ELKHARTLAKE(i915) && (pll->info->id == DPLL_ID_EHL_DPLL4))
+ if (IS_JSL_EHL(i915) && (pll->info->id == DPLL_ID_EHL_DPLL4))
  return MG_PLL_ENABLE(0);
 
  return CNL_DPLL_ENABLE(pll->info->id);
@@ -3551,7 +3551,7 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state,
  BIT(DPLL_ID_EHL_DPLL4) |
  BIT(DPLL_ID_ICL_DPLL1) |
  BIT(DPLL_ID_ICL_DPLL0);
- } else if (IS_ELKHARTLAKE(dev_priv) && port != PORT_A) {
+ } else if (IS_JSL_EHL(dev_priv) && port != PORT_A) {
  dpll_mask =
  BIT(DPLL_ID_EHL_DPLL4) |
  BIT(DPLL_ID_ICL_DPLL1) |
@@ -3853,7 +3853,7 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
  hw_state->cfgcr1 = intel_de_read(dev_priv,
  TGL_DPLL_CFGCR1(id));
  } else {
- if (IS_ELKHARTLAKE(dev_priv) && id == DPLL_ID_EHL_DPLL4) {
+ if (IS_JSL_EHL(dev_priv) && id == DPLL_ID_EHL_DPLL4) {
  hw_state->cfgcr0 = intel_de_read(dev_priv,
  ICL_DPLL_CFGCR0(4));
  hw_state->cfgcr1 = intel_de_read(dev_priv,
@@ -3902,7 +3902,7 @@ static void icl_dpll_write(struct drm_i915_private *dev_priv,
  cfgcr0_reg = TGL_DPLL_CFGCR0(id);
  cfgcr1_reg = TGL_DPLL_CFGCR1(id);
  } else {
- if (IS_ELKHARTLAKE(dev_priv) && id == DPLL_ID_EHL_DPLL4) {
+ if (IS_JSL_EHL(dev_priv) && id == DPLL_ID_EHL_DPLL4) {
  cfgcr0_reg = ICL_DPLL_CFGCR0(4);
  cfgcr1_reg = ICL_DPLL_CFGCR1(4);
  } else {
@@ -4076,7 +4076,7 @@ static void combo_pll_enable(struct drm_i915_private *dev_priv,
 {
  i915_reg_t enable_reg = intel_combo_pll_enable_reg(dev_priv, pll);
 
- if (IS_ELKHARTLAKE(dev_priv) &&
+ if (IS_JSL_EHL(dev_priv) &&
     pll->info->id == DPLL_ID_EHL_DPLL4) {
 
  /*
@@ -4189,7 +4189,7 @@ static void combo_pll_disable(struct drm_i915_private *dev_priv,
 
  icl_pll_disable(dev_priv, pll, enable_reg);
 
- if (IS_ELKHARTLAKE(dev_priv) &&
+ if (IS_JSL_EHL(dev_priv) &&
     pll->info->id == DPLL_ID_EHL_DPLL4)
  intel_display_power_put(dev_priv, POWER_DOMAIN_DPLL_DC_OFF,
  pll->wakeref);
@@ -4356,7 +4356,7 @@ void intel_shared_dpll_init(struct drm_device *dev)
  dpll_mgr = &rkl_pll_mgr;
  else if (INTEL_GEN(dev_priv) >= 12)
  dpll_mgr = &tgl_pll_mgr;
- else if (IS_ELKHARTLAKE(dev_priv))
+ else if (IS_JSL_EHL(dev_priv))
  dpll_mgr = &ehl_pll_mgr;
  else if (INTEL_GEN(dev_priv) >= 11)
  dpll_mgr = &icl_pll_mgr;
@@ -4498,7 +4498,7 @@ static void readout_dpll_hw_state(struct drm_i915_private *i915,
  pll->on = pll->info->funcs->get_hw_state(i915, pll,
  &pll->state.hw_state);
 
- if (IS_ELKHARTLAKE(i915) && pll->on &&
+ if (IS_JSL_EHL(i915) && pll->on &&
     pll->info->id == DPLL_ID_EHL_DPLL4) {
  pll->wakeref = intel_display_power_get(i915,
        POWER_DOMAIN_DPLL_DC_OFF);
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index f1c039e1b5ad..8a72e0fe34ca 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -169,7 +169,7 @@ static void gen11_sseu_info_init(struct intel_gt *gt)
  u8 eu_en;
  u8 s_en;
 
- if (IS_ELKHARTLAKE(gt->i915))
+ if (IS_JSL_EHL(gt->i915))
  intel_sseu_set_info(sseu, 1, 4, 8);
  else
  intel_sseu_set_info(sseu, 1, 8, 8);
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 4a3bde7c9f21..3ec2a98d187e 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1214,7 +1214,7 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 
  /* Wa_1607087056:icl,ehl,jsl */
  if (IS_ICELAKE(i915) ||
-    IS_EHL_REVID(i915, EHL_REVID_A0, EHL_REVID_A0)) {
+ IS_JSL_EHL_REVID(i915, EHL_REVID_A0, EHL_REVID_A0)) {
  wa_write_or(wal,
     SLICE_UNIT_LEVEL_CLKGATE,
     L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
@@ -1841,7 +1841,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
     GEN12_FF_TESSELATION_DOP_GATE_DISABLE);
 
  /* Wa_22010271021:ehl */
- if (IS_ELKHARTLAKE(i915))
+ if (IS_JSL_EHL(i915))
  wa_masked_en(wal,
      GEN9_CS_DEBUG_MODE1,
      FF_DOP_CLOCK_GATE_DISABLE);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 80e8b6c3bc8c..037bcaf3c8b5 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -53,6 +53,7 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
 #define INTEL_UC_FIRMWARE_DEFS(fw_def, guc_def, huc_def) \
  fw_def(ROCKETLAKE,  0, guc_def(tgl, 35, 2, 0), huc_def(tgl,  7, 5, 0)) \
  fw_def(TIGERLAKE,   0, guc_def(tgl, 35, 2, 0), huc_def(tgl,  7, 5, 0)) \
+ fw_def(JASPERLAKE,  0, guc_def(ehl, 33, 0, 4), huc_def(ehl,  9, 0, 0)) \
  fw_def(ELKHARTLAKE, 0, guc_def(ehl, 33, 0, 4), huc_def(ehl,  9, 0, 0)) \
  fw_def(ICELAKE,     0, guc_def(icl, 33, 0, 0), huc_def(icl,  9, 0, 0)) \
  fw_def(COMETLAKE,   5, guc_def(cml, 33, 0, 0), huc_def(cml,  4, 0, 0)) \
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3d3dbc5cfb32..a016871690e6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1422,7 +1422,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_COMETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COMETLAKE)
 #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
 #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
-#define IS_ELKHARTLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
+#define IS_JSL_EHL(dev_priv) (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE) || \
+ IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE))
 #define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
 #define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
 #define IS_DG1(dev_priv)        IS_PLATFORM(dev_priv, INTEL_DG1)
@@ -1563,8 +1564,8 @@ extern const struct i915_rev_steppings kbl_revids[];
 
 #define EHL_REVID_A0            0x0
 
-#define IS_EHL_REVID(p, since, until) \
- (IS_ELKHARTLAKE(p) && IS_REVID(p, since, until))
+#define IS_JSL_EHL_REVID(p, since, until) \
+ (IS_JSL_EHL(p) && IS_REVID(p, since, until))
 
 enum {
  TGL_REVID_A0,
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index e16ec21e269f..4bae14b43f8b 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -847,6 +847,14 @@ static const struct intel_device_info ehl_info = {
  .ppgtt_size = 36,
 };
 
+static const struct intel_device_info jsl_info = {
+ GEN11_FEATURES,
+ PLATFORM(INTEL_JASPERLAKE),
+ .require_force_probe = 1,
+ .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
+ .ppgtt_size = 36,
+};
+
 #define GEN12_FEATURES \
  GEN11_FEATURES, \
  GEN(12), \
@@ -985,6 +993,7 @@ static const struct pci_device_id pciidlist[] = {
  INTEL_CNL_IDS(&cnl_info),
  INTEL_ICL_11_IDS(&icl_info),
  INTEL_EHL_IDS(&ehl_info),
+ INTEL_JSL_IDS(&jsl_info),
  INTEL_TGL_12_IDS(&tgl_info),
  INTEL_RKL_IDS(&rkl_info),
  {0, 0, 0}
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index adc836f15fde..e67cec8fa2aa 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -62,6 +62,7 @@ static const char * const platform_names[] = {
  PLATFORM_NAME(CANNONLAKE),
  PLATFORM_NAME(ICELAKE),
  PLATFORM_NAME(ELKHARTLAKE),
+ PLATFORM_NAME(JASPERLAKE),
  PLATFORM_NAME(TIGERLAKE),
  PLATFORM_NAME(ROCKETLAKE),
  PLATFORM_NAME(DG1),
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 6a3d607218aa..d92fa041c700 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -79,6 +79,7 @@ enum intel_platform {
  /* gen11 */
  INTEL_ICELAKE,
  INTEL_ELKHARTLAKE,
+ INTEL_JASPERLAKE,
  /* gen12 */
  INTEL_TIGERLAKE,
  INTEL_ROCKETLAKE,
diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c
index 6c97192e9ca8..f31c0dabd0cc 100644
--- a/drivers/gpu/drm/i915/intel_pch.c
+++ b/drivers/gpu/drm/i915/intel_pch.c
@@ -115,7 +115,7 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
  return PCH_ICP;
  case INTEL_PCH_MCC_DEVICE_ID_TYPE:
  drm_dbg_kms(&dev_priv->drm, "Found Mule Creek Canyon PCH\n");
- drm_WARN_ON(&dev_priv->drm, !IS_ELKHARTLAKE(dev_priv));
+ drm_WARN_ON(&dev_priv->drm, !IS_JSL_EHL(dev_priv));
  return PCH_MCC;
  case INTEL_PCH_TGP_DEVICE_ID_TYPE:
  case INTEL_PCH_TGP2_DEVICE_ID_TYPE:
@@ -126,7 +126,7 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
  case INTEL_PCH_JSP_DEVICE_ID_TYPE:
  case INTEL_PCH_JSP2_DEVICE_ID_TYPE:
  drm_dbg_kms(&dev_priv->drm, "Found Jasper Lake PCH\n");
- drm_WARN_ON(&dev_priv->drm, !IS_ELKHARTLAKE(dev_priv));
+ drm_WARN_ON(&dev_priv->drm, !IS_JSL_EHL(dev_priv));
  return PCH_JSP;
  default:
  return PCH_NONE;
@@ -157,7 +157,7 @@ intel_virt_detect_pch(const struct drm_i915_private *dev_priv)
 
  if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv))
  id = INTEL_PCH_TGP_DEVICE_ID_TYPE;
- else if (IS_ELKHARTLAKE(dev_priv))
+ else if (IS_JSL_EHL(dev_priv))
  id = INTEL_PCH_MCC_DEVICE_ID_TYPE;
  else if (IS_ICELAKE(dev_priv))
  id = INTEL_PCH_ICP_DEVICE_ID_TYPE;
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 7eeecb07c9a1..1b5e09cfa11e 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -579,15 +579,18 @@
  INTEL_VGA_DEVICE(0x8A51, info), \
  INTEL_VGA_DEVICE(0x8A5D, info)
 
-/* EHL/JSL */
+/* EHL */
 #define INTEL_EHL_IDS(info) \
  INTEL_VGA_DEVICE(0x4500, info), \
  INTEL_VGA_DEVICE(0x4571, info), \
  INTEL_VGA_DEVICE(0x4551, info), \
  INTEL_VGA_DEVICE(0x4541, info), \
- INTEL_VGA_DEVICE(0x4E71, info), \
  INTEL_VGA_DEVICE(0x4557, info), \
- INTEL_VGA_DEVICE(0x4555, info), \
+ INTEL_VGA_DEVICE(0x4555, info)
+
+/* JSL */
+#define INTEL_JSL_IDS(info) \
+ INTEL_VGA_DEVICE(0x4E71, info), \
  INTEL_VGA_DEVICE(0x4E61, info), \
  INTEL_VGA_DEVICE(0x4E57, info), \
  INTEL_VGA_DEVICE(0x4E55, info), \
--
2.25.1


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[PATCH 07/10][SRU][OEM-5.10] drm/i915: Add PORT_TCn aliases to enum port

AceLan Kao
In reply to this post by AceLan Kao
From: Ville Syrjälä <[hidden email]>

BugLink: https://bugs.launchpad.net/bugs/1909457

Since tgl the DDIs have been named A,B,C,TC1,TC2,TC3...
Add the appropriate enum values for the TC DDIs to enum port.

v2: Deal with rkl and dg1

Reviewed-by: Lucas De Marchi <[hidden email]>
Signed-off-by: Ville Syrjälä <[hidden email]>
Link: https://patchwork.freedesktop.org/patch/msgid/20201028213323.5423-3-ville.syrjala@...
(cherry picked from commit 1d8ca002456b6c504b0af2d159c4776ba6b1ad81)
Signed-off-by: Chia-Lin Kao (AceLan) <[hidden email]>
---
 drivers/gpu/drm/i915/display/intel_bios.c    | 10 +++----
 drivers/gpu/drm/i915/display/intel_ddi.c     | 12 ++++-----
 drivers/gpu/drm/i915/display/intel_display.c | 28 ++++++++++----------
 drivers/gpu/drm/i915/display/intel_display.h |  8 ++++++
 4 files changed, 32 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 74679ccf99fc..a3aa8fbd9714 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1663,17 +1663,15 @@ static enum port dvo_port_to_port(struct drm_i915_private *dev_priv,
  [PORT_I] = { DVO_PORT_HDMII, DVO_PORT_DPI, -1 },
  };
  /*
- * Bspec lists the ports as A, B, C, D - however internally in our
- * driver we keep them as PORT_A, PORT_B, PORT_D and PORT_E so the
- * registers in Display Engine match the right offsets. Apply the
- * mapping here to translate from VBT to internal convention.
+ * RKL VBT uses PHY based mapping. Combo PHYs A,B,C,D
+ * map to DDI A,B,TC1,TC2 respectively.
  */
  static const int rkl_port_mapping[][3] = {
  [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 },
  [PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 },
  [PORT_C] = { -1 },
- [PORT_D] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
- [PORT_E] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
+ [PORT_TC1] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
+ [PORT_TC2] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
  };
 
  if (IS_ROCKETLAKE(dev_priv))
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 4f5607a2bcfe..caad1fcb4096 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -5062,8 +5062,8 @@ static bool hti_uses_phy(struct drm_i915_private *i915, enum phy phy)
 static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv,
  enum port port)
 {
- if (port >= PORT_D)
- return HPD_PORT_C + port - PORT_D;
+ if (port >= PORT_TC1)
+ return HPD_PORT_C + port - PORT_TC1;
  else
  return HPD_PORT_A + port - PORT_A;
 }
@@ -5071,8 +5071,8 @@ static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv,
 static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv,
  enum port port)
 {
- if (port >= PORT_D)
- return HPD_PORT_TC1 + port - PORT_D;
+ if (port >= PORT_TC1)
+ return HPD_PORT_TC1 + port - PORT_TC1;
  else
  return HPD_PORT_A + port - PORT_A;
 }
@@ -5083,8 +5083,8 @@ static enum hpd_pin rkl_hpd_pin(struct drm_i915_private *dev_priv,
  if (HAS_PCH_TGP(dev_priv))
  return tgl_hpd_pin(dev_priv, port);
 
- if (port >= PORT_D)
- return HPD_PORT_C + port - PORT_D;
+ if (port >= PORT_TC1)
+ return HPD_PORT_C + port - PORT_TC1;
  else
  return HPD_PORT_A + port - PORT_A;
 }
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index c1b90c1e590d..6ca4b6f16091 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7297,12 +7297,12 @@ bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
 
 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
 {
- if (IS_ROCKETLAKE(i915) && port >= PORT_D)
- return (enum phy)port - 1;
+ if (IS_ROCKETLAKE(i915) && port >= PORT_TC1)
+ return PHY_C + port - PORT_TC1;
  else if (IS_JSL_EHL(i915) && port == PORT_D)
  return PHY_A;
 
- return (enum phy)port;
+ return PHY_A + port - PORT_A;
 }
 
 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
@@ -7311,9 +7311,9 @@ enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
  return PORT_TC_NONE;
 
  if (INTEL_GEN(dev_priv) >= 12)
- return port - PORT_D;
-
- return port - PORT_C;
+ return TC_PORT_1 + port - PORT_TC1;
+ else
+ return TC_PORT_1 + port - PORT_C;
 }
 
 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
@@ -16895,17 +16895,17 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
  if (IS_ROCKETLAKE(dev_priv)) {
  intel_ddi_init(dev_priv, PORT_A);
  intel_ddi_init(dev_priv, PORT_B);
- intel_ddi_init(dev_priv, PORT_D); /* DDI TC1 */
- intel_ddi_init(dev_priv, PORT_E); /* DDI TC2 */
+ intel_ddi_init(dev_priv, PORT_TC1);
+ intel_ddi_init(dev_priv, PORT_TC2);
  } else if (INTEL_GEN(dev_priv) >= 12) {
  intel_ddi_init(dev_priv, PORT_A);
  intel_ddi_init(dev_priv, PORT_B);
- intel_ddi_init(dev_priv, PORT_D);
- intel_ddi_init(dev_priv, PORT_E);
- intel_ddi_init(dev_priv, PORT_F);
- intel_ddi_init(dev_priv, PORT_G);
- intel_ddi_init(dev_priv, PORT_H);
- intel_ddi_init(dev_priv, PORT_I);
+ intel_ddi_init(dev_priv, PORT_TC1);
+ intel_ddi_init(dev_priv, PORT_TC2);
+ intel_ddi_init(dev_priv, PORT_TC2);
+ intel_ddi_init(dev_priv, PORT_TC4);
+ intel_ddi_init(dev_priv, PORT_TC5);
+ intel_ddi_init(dev_priv, PORT_TC6);
  icl_dsi_init(dev_priv);
  } else if (IS_JSL_EHL(dev_priv)) {
  intel_ddi_init(dev_priv, PORT_A);
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index d10b7c8cde3f..631cee4bc30a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -207,6 +207,14 @@ enum port {
  PORT_H,
  PORT_I,
 
+ /* tgl+ */
+ PORT_TC1 = PORT_D,
+ PORT_TC2,
+ PORT_TC3,
+ PORT_TC4,
+ PORT_TC5,
+ PORT_TC6,
+
  I915_MAX_PORTS
 };
 
--
2.25.1


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[PATCH 08/10][SRU][OEM-5.10] drm/i915: s/PORT_TC/TC_PORT_/

AceLan Kao
In reply to this post by AceLan Kao
From: Ville Syrjälä <[hidden email]>

BugLink: https://bugs.launchpad.net/bugs/1909457

Make the namespacing for enum tc_port better by adding
the TC_ to the actual enum values.

v2: Drop the extra TC (Lucas)

Reviewed-by: Lucas De Marchi <[hidden email]>
Signed-off-by: Ville Syrjälä <[hidden email]>
Link: https://patchwork.freedesktop.org/patch/msgid/20201028213323.5423-2-ville.syrjala@...
(cherry picked from commit 320c670c048d3b178da6129257e8aee517c81e10)
Signed-off-by: Chia-Lin Kao (AceLan) <[hidden email]>
---
 drivers/gpu/drm/i915/display/intel_display.c |  2 +-
 drivers/gpu/drm/i915/display/intel_display.h | 16 ++--
 drivers/gpu/drm/i915/display/intel_tc.c      |  2 +-
 drivers/gpu/drm/i915/i915_irq.c              | 78 ++++++++++----------
 drivers/gpu/drm/i915/i915_reg.h              | 60 +++++++--------
 5 files changed, 79 insertions(+), 79 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 6ca4b6f16091..9c7a464dd3d6 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7308,7 +7308,7 @@ enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
 {
  if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
- return PORT_TC_NONE;
+ return TC_PORT_NONE;
 
  if (INTEL_GEN(dev_priv) >= 12)
  return TC_PORT_1 + port - PORT_TC1;
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 631cee4bc30a..84d94b78fe10 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -251,14 +251,14 @@ static inline const char *port_identifier(enum port port)
 }
 
 enum tc_port {
- PORT_TC_NONE = -1,
-
- PORT_TC1 = 0,
- PORT_TC2,
- PORT_TC3,
- PORT_TC4,
- PORT_TC5,
- PORT_TC6,
+ TC_PORT_NONE = -1,
+
+ TC_PORT_1 = 0,
+ TC_PORT_2,
+ TC_PORT_3,
+ TC_PORT_4,
+ TC_PORT_5,
+ TC_PORT_6,
 
  I915_MAX_TC_PORTS
 };
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 8f67aef18b2d..1cb548d757e1 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -652,7 +652,7 @@ void intel_tc_port_init(struct intel_digital_port *dig_port, bool is_legacy)
  enum port port = dig_port->base.port;
  enum tc_port tc_port = intel_port_to_tc(i915, port);
 
- if (drm_WARN_ON(&i915->drm, tc_port == PORT_TC_NONE))
+ if (drm_WARN_ON(&i915->drm, tc_port == TC_PORT_NONE))
  return;
 
  snprintf(dig_port->tc_port_name, sizeof(dig_port->tc_port_name),
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 4676ee791950..1a7b8342a5a9 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -132,24 +132,24 @@ static const u32 hpd_bxt[HPD_NUM_PINS] = {
 };
 
 static const u32 hpd_gen11[HPD_NUM_PINS] = {
- [HPD_PORT_TC1] = GEN11_TC_HOTPLUG(PORT_TC1) | GEN11_TBT_HOTPLUG(PORT_TC1),
- [HPD_PORT_TC2] = GEN11_TC_HOTPLUG(PORT_TC2) | GEN11_TBT_HOTPLUG(PORT_TC2),
- [HPD_PORT_TC3] = GEN11_TC_HOTPLUG(PORT_TC3) | GEN11_TBT_HOTPLUG(PORT_TC3),
- [HPD_PORT_TC4] = GEN11_TC_HOTPLUG(PORT_TC4) | GEN11_TBT_HOTPLUG(PORT_TC4),
- [HPD_PORT_TC5] = GEN11_TC_HOTPLUG(PORT_TC5) | GEN11_TBT_HOTPLUG(PORT_TC5),
- [HPD_PORT_TC6] = GEN11_TC_HOTPLUG(PORT_TC6) | GEN11_TBT_HOTPLUG(PORT_TC6),
+ [HPD_PORT_TC1] = GEN11_TC_HOTPLUG(TC_PORT_1) | GEN11_TBT_HOTPLUG(TC_PORT_1),
+ [HPD_PORT_TC2] = GEN11_TC_HOTPLUG(TC_PORT_2) | GEN11_TBT_HOTPLUG(TC_PORT_2),
+ [HPD_PORT_TC3] = GEN11_TC_HOTPLUG(TC_PORT_3) | GEN11_TBT_HOTPLUG(TC_PORT_3),
+ [HPD_PORT_TC4] = GEN11_TC_HOTPLUG(TC_PORT_4) | GEN11_TBT_HOTPLUG(TC_PORT_4),
+ [HPD_PORT_TC5] = GEN11_TC_HOTPLUG(TC_PORT_5) | GEN11_TBT_HOTPLUG(TC_PORT_5),
+ [HPD_PORT_TC6] = GEN11_TC_HOTPLUG(TC_PORT_6) | GEN11_TBT_HOTPLUG(TC_PORT_6),
 };
 
 static const u32 hpd_icp[HPD_NUM_PINS] = {
  [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PORT_A),
  [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PORT_B),
  [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(PORT_C),
- [HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(PORT_TC1),
- [HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(PORT_TC2),
- [HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(PORT_TC3),
- [HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(PORT_TC4),
- [HPD_PORT_TC5] = SDE_TC_HOTPLUG_ICP(PORT_TC5),
- [HPD_PORT_TC6] = SDE_TC_HOTPLUG_ICP(PORT_TC6),
+ [HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(TC_PORT_1),
+ [HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(TC_PORT_2),
+ [HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(TC_PORT_3),
+ [HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(TC_PORT_4),
+ [HPD_PORT_TC5] = SDE_TC_HOTPLUG_ICP(TC_PORT_5),
+ [HPD_PORT_TC6] = SDE_TC_HOTPLUG_ICP(TC_PORT_6),
 };
 
 static const u32 hpd_sde_dg1[HPD_NUM_PINS] = {
@@ -1041,17 +1041,17 @@ static bool gen11_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
 {
  switch (pin) {
  case HPD_PORT_TC1:
- return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC1);
+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_1);
  case HPD_PORT_TC2:
- return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC2);
+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_2);
  case HPD_PORT_TC3:
- return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC3);
+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_3);
  case HPD_PORT_TC4:
- return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC4);
+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_4);
  case HPD_PORT_TC5:
- return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC5);
+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_5);
  case HPD_PORT_TC6:
- return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC6);
+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_6);
  default:
  return false;
  }
@@ -1091,17 +1091,17 @@ static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
 {
  switch (pin) {
  case HPD_PORT_TC1:
- return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1);
+ return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_1);
  case HPD_PORT_TC2:
- return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2);
+ return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_2);
  case HPD_PORT_TC3:
- return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3);
+ return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_3);
  case HPD_PORT_TC4:
- return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4);
+ return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_4);
  case HPD_PORT_TC5:
- return val & ICP_TC_HPD_LONG_DETECT(PORT_TC5);
+ return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_5);
  case HPD_PORT_TC6:
- return val & ICP_TC_HPD_LONG_DETECT(PORT_TC6);
+ return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_6);
  default:
  return false;
  }
@@ -1866,7 +1866,7 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
  tc_hotplug_trigger = 0;
  } else if (HAS_PCH_MCC(dev_priv)) {
  ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
- tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_ICP(PORT_TC1);
+ tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_ICP(TC_PORT_1);
  } else {
  drm_WARN(&dev_priv->drm, !HAS_PCH_ICP(dev_priv),
  "Unrecognized PCH type 0x%x\n",
@@ -3096,7 +3096,7 @@ static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv,
 static void mcc_hpd_irq_setup(struct drm_i915_private *dev_priv)
 {
  icp_hpd_irq_setup(dev_priv,
-  ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE(PORT_TC1));
+  ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE(TC_PORT_1));
 }
 
 /*
@@ -3121,21 +3121,21 @@ static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
  u32 hotplug;
 
  hotplug = I915_READ(GEN11_TC_HOTPLUG_CTL);
- hotplug |= GEN11_HOTPLUG_CTL_ENABLE(PORT_TC1) |
-   GEN11_HOTPLUG_CTL_ENABLE(PORT_TC2) |
-   GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3) |
-   GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4) |
-   GEN11_HOTPLUG_CTL_ENABLE(PORT_TC5) |
-   GEN11_HOTPLUG_CTL_ENABLE(PORT_TC6);
+ hotplug |= GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_1) |
+   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_2) |
+   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_3) |
+   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_4) |
+   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_5) |
+   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_6);
  I915_WRITE(GEN11_TC_HOTPLUG_CTL, hotplug);
 
  hotplug = I915_READ(GEN11_TBT_HOTPLUG_CTL);
- hotplug |= GEN11_HOTPLUG_CTL_ENABLE(PORT_TC1) |
-   GEN11_HOTPLUG_CTL_ENABLE(PORT_TC2) |
-   GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3) |
-   GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4) |
-   GEN11_HOTPLUG_CTL_ENABLE(PORT_TC5) |
-   GEN11_HOTPLUG_CTL_ENABLE(PORT_TC6);
+ hotplug |= GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_1) |
+   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_2) |
+   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_3) |
+   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_4) |
+   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_5) |
+   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_6);
  I915_WRITE(GEN11_TBT_HOTPLUG_CTL, hotplug);
 }
 
@@ -3508,7 +3508,7 @@ static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
  icp_ddi_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK);
  } else if (HAS_PCH_MCC(dev_priv)) {
  icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK);
- icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE(PORT_TC1));
+ icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE(TC_PORT_1));
  } else {
  icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK);
  icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE_MASK);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fef108d7e22e..e0aec128c2fb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7762,19 +7762,19 @@ enum {
 #define GEN11_DE_HPD_IIR _MMIO(0x44478)
 #define GEN11_DE_HPD_IER _MMIO(0x4447c)
 #define  GEN11_TC_HOTPLUG(tc_port) (1 << ((tc_port) + 16))
-#define  GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC_HOTPLUG(PORT_TC6) | \
- GEN11_TC_HOTPLUG(PORT_TC5) | \
- GEN11_TC_HOTPLUG(PORT_TC4) | \
- GEN11_TC_HOTPLUG(PORT_TC3) | \
- GEN11_TC_HOTPLUG(PORT_TC2) | \
- GEN11_TC_HOTPLUG(PORT_TC1))
+#define  GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC_HOTPLUG(TC_PORT_6) | \
+ GEN11_TC_HOTPLUG(TC_PORT_5) | \
+ GEN11_TC_HOTPLUG(TC_PORT_4) | \
+ GEN11_TC_HOTPLUG(TC_PORT_3) | \
+ GEN11_TC_HOTPLUG(TC_PORT_2) | \
+ GEN11_TC_HOTPLUG(TC_PORT_1))
 #define  GEN11_TBT_HOTPLUG(tc_port) (1 << (tc_port))
-#define  GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT_HOTPLUG(PORT_TC6) | \
- GEN11_TBT_HOTPLUG(PORT_TC5) | \
- GEN11_TBT_HOTPLUG(PORT_TC4) | \
- GEN11_TBT_HOTPLUG(PORT_TC3) | \
- GEN11_TBT_HOTPLUG(PORT_TC2) | \
- GEN11_TBT_HOTPLUG(PORT_TC1))
+#define  GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT_HOTPLUG(TC_PORT_6) | \
+ GEN11_TBT_HOTPLUG(TC_PORT_5) | \
+ GEN11_TBT_HOTPLUG(TC_PORT_4) | \
+ GEN11_TBT_HOTPLUG(TC_PORT_3) | \
+ GEN11_TBT_HOTPLUG(TC_PORT_2) | \
+ GEN11_TBT_HOTPLUG(TC_PORT_1))
 
 #define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030)
 #define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038)
@@ -8214,19 +8214,19 @@ enum {
 #define SDE_DDI_HOTPLUG_ICP(port) (1 << ((port) + 16))
 #define SDE_DDI_MASK_ICP (SDE_DDI_HOTPLUG_ICP(PORT_B) | \
  SDE_DDI_HOTPLUG_ICP(PORT_A))
-#define SDE_TC_MASK_ICP (SDE_TC_HOTPLUG_ICP(PORT_TC4) | \
- SDE_TC_HOTPLUG_ICP(PORT_TC3) | \
- SDE_TC_HOTPLUG_ICP(PORT_TC2) | \
- SDE_TC_HOTPLUG_ICP(PORT_TC1))
+#define SDE_TC_MASK_ICP (SDE_TC_HOTPLUG_ICP(TC_PORT_4) | \
+ SDE_TC_HOTPLUG_ICP(TC_PORT_3) | \
+ SDE_TC_HOTPLUG_ICP(TC_PORT_2) | \
+ SDE_TC_HOTPLUG_ICP(TC_PORT_1))
 #define SDE_DDI_MASK_TGP (SDE_DDI_HOTPLUG_ICP(PORT_C) | \
  SDE_DDI_HOTPLUG_ICP(PORT_B) | \
  SDE_DDI_HOTPLUG_ICP(PORT_A))
-#define SDE_TC_MASK_TGP (SDE_TC_HOTPLUG_ICP(PORT_TC6) | \
- SDE_TC_HOTPLUG_ICP(PORT_TC5) | \
- SDE_TC_HOTPLUG_ICP(PORT_TC4) | \
- SDE_TC_HOTPLUG_ICP(PORT_TC3) | \
- SDE_TC_HOTPLUG_ICP(PORT_TC2) | \
- SDE_TC_HOTPLUG_ICP(PORT_TC1))
+#define SDE_TC_MASK_TGP (SDE_TC_HOTPLUG_ICP(TC_PORT_6) | \
+ SDE_TC_HOTPLUG_ICP(TC_PORT_5) | \
+ SDE_TC_HOTPLUG_ICP(TC_PORT_4) | \
+ SDE_TC_HOTPLUG_ICP(TC_PORT_3) | \
+ SDE_TC_HOTPLUG_ICP(TC_PORT_2) | \
+ SDE_TC_HOTPLUG_ICP(TC_PORT_1))
 #define SDE_DDI_MASK_DG1 (SDE_DDI_HOTPLUG_ICP(PORT_D) | \
  SDE_DDI_HOTPLUG_ICP(PORT_C) | \
  SDE_DDI_HOTPLUG_ICP(PORT_B) | \
@@ -8420,15 +8420,15 @@ enum {
 
 #define ICP_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \
  SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A))
-#define ICP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(PORT_TC4) | \
- ICP_TC_HPD_ENABLE(PORT_TC3) | \
- ICP_TC_HPD_ENABLE(PORT_TC2) | \
- ICP_TC_HPD_ENABLE(PORT_TC1))
+#define ICP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(TC_PORT_4) | \
+ ICP_TC_HPD_ENABLE(TC_PORT_3) | \
+ ICP_TC_HPD_ENABLE(TC_PORT_2) | \
+ ICP_TC_HPD_ENABLE(TC_PORT_1))
 #define TGP_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_C) | \
  SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \
  SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A))
-#define TGP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(PORT_TC6) | \
- ICP_TC_HPD_ENABLE(PORT_TC5) | \
+#define TGP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(TC_PORT_6) | \
+ ICP_TC_HPD_ENABLE(TC_PORT_5) | \
  ICP_TC_HPD_ENABLE_MASK)
 #define DG1_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_D) | \
  SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_C) | \
@@ -10285,9 +10285,9 @@ enum skl_power_gate {
 #define ICL_DPCLKA_CFGCR0 _MMIO(0x164280)
 #define  ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24))
 #define  RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10)
-#define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < PORT_TC4 ? \
+#define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < TC_PORT_4 ? \
        (tc_port) + 12 : \
-       (tc_port) - PORT_TC4 + 21))
+       (tc_port) - TC_PORT_4 + 21))
 #define  ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2)
 #define  ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
 #define  ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
--
2.25.1


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[PATCH 09/10][SRU][OEM-5.10][Unstable] drm/i915/rkl: new rkl ddc map for different PCH

AceLan Kao
In reply to this post by AceLan Kao
From: Lee Shawn C <[hidden email]>

BugLink: https://bugs.launchpad.net/bugs/1909457

After boot into kernel. Driver configured ddc pin mapping based on
predefined table in parse_ddi_port(). Now driver configure rkl
ddc pin mapping depends on icp_ddc_pin_map[]. Then this table will
give incorrect gmbus port number to cause HDMI can't work.

Refer to commit cd0a89527d06 ("drm/i915/rkl: Add DDC pin mapping").
Create two ddc pin table for rkl TGP and CMP pch. Then HDMI can
works properly on rkl.

v2: update patch based on latest dinq branch.
v3: update ddc table for RKL+TGP sku.
    RKL+CNP sku will load cnp_ddc_pin_map[] setting.
v4: modify the if/else judgment to avoid nesting.
v5: fix typo in v4.

Cc: Matt Roper <[hidden email]>
Cc: Aditya Swarup <[hidden email]>
Cc: Anusha Srivatsa <[hidden email]>
Cc: Jani Nikula <[hidden email]>
Cc: Cooper Chiou <[hidden email]>
Cc: Khaled Almahallawy <[hidden email]>
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2577
Signed-off-by: Lee Shawn C <[hidden email]>
Reviewed-by: Matt Roper <[hidden email]>
Signed-off-by: Lyude Paul <[hidden email]>
Link: https://patchwork.freedesktop.org/patch/msgid/20201117142629.28729-1-shawn.c.lee@...
(cherry picked from commit 956aee8fa366cfd9d693aa6e7ef822b775980c01
drm-next)
Signed-off-by: Chia-Lin Kao (AceLan) <[hidden email]>
---
 drivers/gpu/drm/i915/display/intel_bios.c     | 10 ++++++++++
 drivers/gpu/drm/i915/display/intel_vbt_defs.h |  2 ++
 2 files changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index a3aa8fbd9714..973672489566 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1598,6 +1598,13 @@ static const u8 icp_ddc_pin_map[] = {
  [TGL_DDC_BUS_PORT_6] = GMBUS_PIN_14_TC6_TGP,
 };
 
+static const u8 rkl_pch_tgp_ddc_pin_map[] = {
+ [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT,
+ [ICL_DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT,
+ [RKL_DDC_BUS_DDI_D] = GMBUS_PIN_9_TC1_ICP,
+ [RKL_DDC_BUS_DDI_E] = GMBUS_PIN_10_TC2_ICP,
+};
+
 static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
 {
  const u8 *ddc_pin_map;
@@ -1605,6 +1612,9 @@ static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
 
  if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) {
  return vbt_pin;
+ } else if (IS_ROCKETLAKE(dev_priv) && INTEL_PCH_TYPE(dev_priv) == PCH_TGP) {
+ ddc_pin_map = rkl_pch_tgp_ddc_pin_map;
+ n_entries = ARRAY_SIZE(rkl_pch_tgp_ddc_pin_map);
  } else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) {
  ddc_pin_map = icp_ddc_pin_map;
  n_entries = ARRAY_SIZE(icp_ddc_pin_map);
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 54bcc6a6947c..1a17ef519d74 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -319,6 +319,8 @@ enum vbt_gmbus_ddi {
  ICL_DDC_BUS_DDI_A = 0x1,
  ICL_DDC_BUS_DDI_B,
  TGL_DDC_BUS_DDI_C,
+ RKL_DDC_BUS_DDI_D = 0x3,
+ RKL_DDC_BUS_DDI_E,
  ICL_DDC_BUS_PORT_1 = 0x4,
  ICL_DDC_BUS_PORT_2,
  ICL_DDC_BUS_PORT_3,
--
2.25.1


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[PATCH 10/10][SRU][OEM-5.10][Unstable] UBUNTU: SAUCE: drm/i915/gen9_bc : Add TGP PCH support

AceLan Kao
In reply to this post by AceLan Kao
From: Tejas Upadhyay <[hidden email]>

BugLink: https://bugs.launchpad.net/bugs/1909457

We have TGP PCH support for Tigerlake and Rocketlake. Similarly
now TGP PCH can be used with Cometlake CPU.

Changes since V3 :
        - Rebased to top drm-tip commit
        - dev_priv replaced with i915 for new API
        - Enable default Port B,C,D detection for TGP && GEN9_BC
Changes since V2 :
        - IS_COMETLAKE replaced with IS_GEN9_BC
        - VBT ddc pin remapping added
        - Added dedicated HPD pin and DDC pin handling API
Changes since V1 :
        - Matched HPD Pin mapping for PORT C and PORT D of CML CPU.

Cc: Matt Roper <[hidden email]>
Cc: Jani Nikula <[hidden email]>
Signed-off-by: Tejas Upadhyay <[hidden email]>
(cherry picked from https://patchwork.freedesktop.org/patch/412664/)
Signed-off-by: Chia-Lin Kao (AceLan) <[hidden email]>
---
 drivers/gpu/drm/i915/display/intel_bios.c    |  9 +++++++++
 drivers/gpu/drm/i915/display/intel_ddi.c     |  7 +++++--
 drivers/gpu/drm/i915/display/intel_display.c |  9 ++++++++-
 drivers/gpu/drm/i915/display/intel_hdmi.c    | 20 ++++++++++++++++++++
 drivers/gpu/drm/i915/intel_pch.c             |  3 ++-
 5 files changed, 44 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 973672489566..368079c451f6 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1605,6 +1605,12 @@ static const u8 rkl_pch_tgp_ddc_pin_map[] = {
  [RKL_DDC_BUS_DDI_E] = GMBUS_PIN_10_TC2_ICP,
 };
 
+static const u8 gen9bc_tgp_ddc_pin_map[] = {
+ [DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT,
+ [DDC_BUS_DDI_C] = GMBUS_PIN_9_TC1_ICP,
+ [DDC_BUS_DDI_D] = GMBUS_PIN_10_TC2_ICP,
+};
+
 static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
 {
  const u8 *ddc_pin_map;
@@ -1615,6 +1621,9 @@ static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
  } else if (IS_ROCKETLAKE(dev_priv) && INTEL_PCH_TYPE(dev_priv) == PCH_TGP) {
  ddc_pin_map = rkl_pch_tgp_ddc_pin_map;
  n_entries = ARRAY_SIZE(rkl_pch_tgp_ddc_pin_map);
+ } else if (HAS_PCH_TGP(dev_priv) && IS_GEN9_BC(dev_priv)) {
+ ddc_pin_map = gen9bc_tgp_ddc_pin_map;
+ n_entries = ARRAY_SIZE(gen9bc_tgp_ddc_pin_map);
  } else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) {
  ddc_pin_map = icp_ddc_pin_map;
  n_entries = ARRAY_SIZE(icp_ddc_pin_map);
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index caad1fcb4096..f033d63768ac 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -5071,7 +5071,9 @@ static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv,
 static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv,
  enum port port)
 {
- if (port >= PORT_TC1)
+ if (IS_GEN9_BC(dev_priv) && port >= PORT_C)
+ return HPD_PORT_TC1 + port - PORT_C;
+ else if (port >= PORT_TC1)
  return HPD_PORT_TC1 + port - PORT_TC1;
  else
  return HPD_PORT_A + port - PORT_A;
@@ -5201,7 +5203,8 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
  encoder->hpd_pin = dg1_hpd_pin(dev_priv, port);
  else if (IS_ROCKETLAKE(dev_priv))
  encoder->hpd_pin = rkl_hpd_pin(dev_priv, port);
- else if (INTEL_GEN(dev_priv) >= 12)
+ else if (INTEL_GEN(dev_priv) >= 12 || (IS_GEN9_BC(dev_priv) &&
+       HAS_PCH_TGP(dev_priv)))
  encoder->hpd_pin = tgl_hpd_pin(dev_priv, port);
  else if (IS_JSL_EHL(dev_priv))
  encoder->hpd_pin = ehl_hpd_pin(dev_priv, port);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 9c7a464dd3d6..97afa1fb515a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -16958,7 +16958,14 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
 
  /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP
  * register */
- found = intel_de_read(dev_priv, SFUSE_STRAP);
+ if (HAS_PCH_TGP(dev_priv)) {
+ /* W/A due to lack of STRAP config on TGP PCH*/
+ found = (SFUSE_STRAP_DDIB_DETECTED |
+ SFUSE_STRAP_DDIC_DETECTED |
+ SFUSE_STRAP_DDID_DETECTED);
+ } else {
+ found = intel_de_read(dev_priv, SFUSE_STRAP);
+ }
 
  if (found & SFUSE_STRAP_DDIB_DETECTED)
  intel_ddi_init(dev_priv, PORT_B);
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 866bc6b4b73c..52eac30655b6 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -3145,6 +3145,24 @@ static u8 rkl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
  return GMBUS_PIN_1_BXT + phy;
 }
 
+static u8 gen9bc_port_to_ddc_pin(struct drm_i915_private *i915, enum port port)
+{
+ enum phy phy = intel_port_to_phy(i915, port);
+
+ drm_WARN_ON(&i915->drm, port == PORT_A);
+
+ /*
+ * Pin mapping for GEN9 BC depends on which PCH is present.  With TGP,
+ * final two outputs use type-c pins, even though they're actually
+ * combo outputs.  With CMP, the traditional DDI A-D pins are used for
+ * all outputs.
+ */
+ if (INTEL_PCH_TYPE(i915) >= PCH_TGP && phy >= PHY_C)
+ return GMBUS_PIN_9_TC1_ICP + phy - PHY_C;
+
+ return GMBUS_PIN_1_BXT + phy;
+}
+
 static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
 {
  return intel_port_to_phy(dev_priv, port) + 1;
@@ -3191,6 +3209,8 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
  ddc_pin = dg1_port_to_ddc_pin(dev_priv, port);
  else if (IS_ROCKETLAKE(dev_priv))
  ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
+ else if (IS_GEN9_BC(dev_priv) && HAS_PCH_TGP(dev_priv))
+ ddc_pin = gen9bc_port_to_ddc_pin(dev_priv, port);
  else if (HAS_PCH_MCC(dev_priv))
  ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
  else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c
index f31c0dabd0cc..c1bc2d032360 100644
--- a/drivers/gpu/drm/i915/intel_pch.c
+++ b/drivers/gpu/drm/i915/intel_pch.c
@@ -121,7 +121,8 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
  case INTEL_PCH_TGP2_DEVICE_ID_TYPE:
  drm_dbg_kms(&dev_priv->drm, "Found Tiger Lake LP PCH\n");
  drm_WARN_ON(&dev_priv->drm, !IS_TIGERLAKE(dev_priv) &&
-    !IS_ROCKETLAKE(dev_priv));
+    !IS_ROCKETLAKE(dev_priv) &&
+    !IS_GEN9_BC(dev_priv));
  return PCH_TGP;
  case INTEL_PCH_JSP_DEVICE_ID_TYPE:
  case INTEL_PCH_JSP2_DEVICE_ID_TYPE:
--
2.25.1


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APPLIED [OEM-5.10] Re: [PATCH 00/10][SRU][OEM-5.10][Unstable] Support CML-S CPU + TGP PCH

Timo Aaltonen-6
In reply to this post by AceLan Kao
On 18.1.2021 16.25, AceLan Kao wrote:

> From: "Chia-Lin Kao (AceLan)" <[hidden email]>
>
> https://bugs.launchpad.net/bugs/1909457
>
> [Impact]
> i915 driver gives below warnings that CML-S GPU doesn't work with TGL/RKL
> PCH, and the screen is blank.
>
> kernel: i915 0000:00:02.0: drm_WARN_ON(!IS_PLATFORM(dev_priv, INTEL_TIGERLAKE) && !IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE))
>
> [Fix]
> Intel provides us a new patch for this issue
> https://patchwork.freedesktop.org/patch/412664/
>
> [Test]
> Verified on new Dell platforms.
>
> [Where problems could occur]
> The first commit reverts the patch that didn't find its way to upstream.
> The second to forth commits are to enable DG1 which applied for solving conflicts.
> The fifth and sixth commit splits code for EHL and JSL.
> The seventh and eighth commits rename enums, no function changes.
> The ninth commit is the newer version of the first reverted commit.
> The tenth commit adds CML CPU support on TGP PCH which fixes this issue.
> According to the above explanation,
> 1. the DG1 in newly enabled by commits 2 to 4, no regression could occur,
> 2. the EHL and JSL commits are pretty simple and straightforward, should be safe to include,
> 3. the first commit is equivalence to the ninth commit
> 4. the tenth commit is pretty simple to add GEN9 into flow control,
> so I think there should be no problems could occur from this patchset.
>
> Chia-Lin Kao (AceLan) (1):
>    Revert "UBUNTU: SAUCE: drm/i915/rkl: new rkl ddc map for different
>      PCH"
>
> José Roberto de Souza (1):
>    drm/i915/display/ehl: Limit eDP to HBR2
>
> Lee Shawn C (1):
>    drm/i915/rkl: new rkl ddc map for different PCH
>
> Lucas De Marchi (2):
>    drm/i915/dg1: gmbus pin mapping
>    drm/i915/dg1: add hpd interrupt handling
>
> Matt Roper (1):
>    drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D
>
> Tejas Upadhyay (2):
>    drm/i915/jsl: Split EHL/JSL platform info and PCI ids
>    UBUNTU: SAUCE: drm/i915/gen9_bc : Add TGP PCH support
>
> Ville Syrjälä (2):
>    drm/i915: Add PORT_TCn aliases to enum port
>    drm/i915: s/PORT_TC/TC_PORT_/
>
>   drivers/gpu/drm/i915/display/icl_dsi.c        |   4 +-
>   drivers/gpu/drm/i915/display/intel_bios.c     |  35 +++---
>   drivers/gpu/drm/i915/display/intel_cdclk.c    |   4 +-
>   .../gpu/drm/i915/display/intel_combo_phy.c    |   9 +-
>   drivers/gpu/drm/i915/display/intel_ddi.c      |  47 ++++---
>   drivers/gpu/drm/i915/display/intel_display.c  |  47 ++++---
>   drivers/gpu/drm/i915/display/intel_display.h  |  24 ++--
>   drivers/gpu/drm/i915/display/intel_dp.c       |  11 +-
>   drivers/gpu/drm/i915/display/intel_dpll_mgr.c |  16 +--
>   drivers/gpu/drm/i915/display/intel_gmbus.c    |  15 ++-
>   drivers/gpu/drm/i915/display/intel_hdmi.c     |  29 ++++-
>   drivers/gpu/drm/i915/display/intel_tc.c       |   2 +-
>   drivers/gpu/drm/i915/gt/intel_sseu.c          |   2 +-
>   drivers/gpu/drm/i915/gt/intel_workarounds.c   |   4 +-
>   drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c      |   1 +
>   drivers/gpu/drm/i915/i915_drv.h               |   7 +-
>   drivers/gpu/drm/i915/i915_irq.c               | 115 +++++++++++-------
>   drivers/gpu/drm/i915/i915_pci.c               |   9 ++
>   drivers/gpu/drm/i915/i915_reg.h               |  68 ++++++-----
>   drivers/gpu/drm/i915/intel_device_info.c      |   1 +
>   drivers/gpu/drm/i915/intel_device_info.h      |   1 +
>   drivers/gpu/drm/i915/intel_pch.c              |   9 +-
>   include/drm/i915_pciids.h                     |   9 +-
>   23 files changed, 299 insertions(+), 170 deletions(-)
>

applied to oem-5.10, thanks

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APPLIED[Unstable]: [PATCH 00/10][SRU][OEM-5.10][Unstable] Support CML-S CPU + TGP PCH

Seth Forshee
In reply to this post by AceLan Kao
On Mon, Jan 18, 2021 at 10:25:54PM +0800, AceLan Kao wrote:

> From: "Chia-Lin Kao (AceLan)" <[hidden email]>
>
> https://bugs.launchpad.net/bugs/1909457
>
> [Impact]
> i915 driver gives below warnings that CML-S GPU doesn't work with TGL/RKL
> PCH, and the screen is blank.
>
> kernel: i915 0000:00:02.0: drm_WARN_ON(!IS_PLATFORM(dev_priv, INTEL_TIGERLAKE) && !IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE))
>
> [Fix]
> Intel provides us a new patch for this issue
> https://patchwork.freedesktop.org/patch/412664/
>
> [Test]
> Verified on new Dell platforms.
>
> [Where problems could occur]
> The first commit reverts the patch that didn't find its way to upstream.
> The second to forth commits are to enable DG1 which applied for solving conflicts.
> The fifth and sixth commit splits code for EHL and JSL.
> The seventh and eighth commits rename enums, no function changes.
> The ninth commit is the newer version of the first reverted commit.
> The tenth commit adds CML CPU support on TGP PCH which fixes this issue.
> According to the above explanation,
> 1. the DG1 in newly enabled by commits 2 to 4, no regression could occur,
> 2. the EHL and JSL commits are pretty simple and straightforward, should be safe to include,
> 3. the first commit is equivalence to the ninth commit
> 4. the tenth commit is pretty simple to add GEN9 into flow control,
> so I think there should be no problems could occur from this patchset.

Applied to unstable/master, thanks.

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