[PATCH 1/2] [Zesty] UBUNTU: SAUCE: powerpc/mm/radix: Don't do page walk cache flush when doing full mm flush

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[PATCH 1/2] [Zesty] UBUNTU: SAUCE: powerpc/mm/radix: Don't do page walk cache flush when doing full mm flush

Breno Leitao
From: "Aneesh Kumar K.V" <[hidden email]>

BugLink: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1681429

For fullmm tlb flush, we do a flush with RIC_FLUSH_ALL which will invalidate all
related caches (radix__tlb_flush()). Hence the pwc flush is not needed.

Signed-off-by: Aneesh Kumar K.V <[hidden email]>
Acked-by: Anton Blanchard <[hidden email]>
Signed-off-by: Breno Leitao <[hidden email]>
---
 arch/powerpc/mm/tlb-radix.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/powerpc/mm/tlb-radix.c b/arch/powerpc/mm/tlb-radix.c
index 952713d6cf04..74f17e3c7cbe 100644
--- a/arch/powerpc/mm/tlb-radix.c
+++ b/arch/powerpc/mm/tlb-radix.c
@@ -129,6 +129,12 @@ void radix__local_flush_tlb_pwc(struct mmu_gather *tlb, unsigned long addr)
 {
  unsigned long pid;
  struct mm_struct *mm = tlb->mm;
+ /*
+ * If we are doing a full mm flush, we will do a tlb flush
+ * with RIC_FLUSH_ALL later.
+ */
+ if (tlb->fullmm)
+ return;
 
  preempt_disable();
 
@@ -195,6 +201,12 @@ void radix__flush_tlb_pwc(struct mmu_gather *tlb, unsigned long addr)
  unsigned long pid;
  struct mm_struct *mm = tlb->mm;
 
+ /*
+ * If we are doing a full mm flush, we will do a tlb flush
+ * with RIC_FLUSH_ALL later.
+ */
+ if (tlb->fullmm)
+ return;
  preempt_disable();
 
  pid = mm->context.id;
--
2.11.0


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[PATCH 2/2] [Zesty] UBUNTU: SAUCE: powerpc/mm/radix: Remove unnecessary ptesync

Breno Leitao
From: "Aneesh Kumar K.V" <[hidden email]>

BugLink: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1681429

For a tlbiel with pid, we need to issue tlbiel with set number encoded. We
don't need to do ptesync for each of those. Instead we need one for the entire
tlbiel pid operation.

Signed-off-by: Benjamin Herrenschmidt <[hidden email]>
Signed-off-by: Aneesh Kumar K.V <[hidden email]>
Acked-by: Anton Blanchard <[hidden email]>
Signed-off-by: Breno Leitao <[hidden email]>
---
 arch/powerpc/mm/tlb-radix.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/mm/tlb-radix.c b/arch/powerpc/mm/tlb-radix.c
index 74f17e3c7cbe..93c9d8080b2a 100644
--- a/arch/powerpc/mm/tlb-radix.c
+++ b/arch/powerpc/mm/tlb-radix.c
@@ -34,10 +34,8 @@ static inline void __tlbiel_pid(unsigned long pid, int set,
  prs = 1; /* process scoped */
  r = 1;   /* raidx format */
 
- asm volatile("ptesync": : :"memory");
  asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
      : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
- asm volatile("ptesync": : :"memory");
 }
 
 /*
@@ -47,9 +45,11 @@ static inline void _tlbiel_pid(unsigned long pid, unsigned long ric)
 {
  int set;
 
+ asm volatile("ptesync": : :"memory");
  for (set = 0; set < POWER9_TLB_SETS_RADIX ; set++) {
  __tlbiel_pid(pid, set, ric);
  }
+ asm volatile("ptesync": : :"memory");
  asm volatile(PPC_INVALIDATE_ERAT "; isync" : : :"memory");
 }
 
--
2.11.0


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ACK: [PATCH 1/2] [Zesty] UBUNTU: SAUCE: powerpc/mm/radix: Don't do page walk cache flush when doing full mm flush

Seth Forshee
In reply to this post by Breno Leitao
On Mon, Apr 10, 2017 at 10:23:45AM -0300, Breno Leitao wrote:

> From: "Aneesh Kumar K.V" <[hidden email]>
>
> BugLink: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1681429
>
> For fullmm tlb flush, we do a flush with RIC_FLUSH_ALL which will invalidate all
> related caches (radix__tlb_flush()). Hence the pwc flush is not needed.
>
> Signed-off-by: Aneesh Kumar K.V <[hidden email]>
> Acked-by: Anton Blanchard <[hidden email]>
> Signed-off-by: Breno Leitao <[hidden email]>

Both patches are straight-forward and limited in scope. For both:

Acked-by: Seth Forshee <[hidden email]>

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Re: [PATCH 1/2] [Zesty] UBUNTU: SAUCE: powerpc/mm/radix: Don't do page walk cache flush when doing full mm flush

Colin Ian King-2
In reply to this post by Breno Leitao
On 10/04/17 14:23, Breno Leitao wrote:

> From: "Aneesh Kumar K.V" <[hidden email]>
>
> BugLink: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1681429
>
> For fullmm tlb flush, we do a flush with RIC_FLUSH_ALL which will invalidate all
> related caches (radix__tlb_flush()). Hence the pwc flush is not needed.
>
> Signed-off-by: Aneesh Kumar K.V <[hidden email]>
> Acked-by: Anton Blanchard <[hidden email]>
> Signed-off-by: Breno Leitao <[hidden email]>
> ---
>  arch/powerpc/mm/tlb-radix.c | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
>
> diff --git a/arch/powerpc/mm/tlb-radix.c b/arch/powerpc/mm/tlb-radix.c
> index 952713d6cf04..74f17e3c7cbe 100644
> --- a/arch/powerpc/mm/tlb-radix.c
> +++ b/arch/powerpc/mm/tlb-radix.c
> @@ -129,6 +129,12 @@ void radix__local_flush_tlb_pwc(struct mmu_gather *tlb, unsigned long addr)
>  {
>   unsigned long pid;
>   struct mm_struct *mm = tlb->mm;
> + /*
> + * If we are doing a full mm flush, we will do a tlb flush
> + * with RIC_FLUSH_ALL later.
> + */
> + if (tlb->fullmm)
> + return;
>  
>   preempt_disable();
>  
> @@ -195,6 +201,12 @@ void radix__flush_tlb_pwc(struct mmu_gather *tlb, unsigned long addr)
>   unsigned long pid;
>   struct mm_struct *mm = tlb->mm;
>  
> + /*
> + * If we are doing a full mm flush, we will do a tlb flush
> + * with RIC_FLUSH_ALL later.
> + */
> + if (tlb->fullmm)
> + return;
>   preempt_disable();
>  
>   pid = mm->context.id;
>

Patches 1 and 2 are clear optimizations and are arch-specific. Both
appear OK to me.

Acked-by: Colin Ian King <[hidden email]>

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APPLIED: [PATCH 1/2] [Zesty] UBUNTU: SAUCE: powerpc/mm/radix: Don't do page walk cache flush when doing full mm flush

Seth Forshee
In reply to this post by Breno Leitao
Applied to zesty master-next.

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