[PATCH][SRU Bionic] PCI: Add decoding for 16 GT/s link speed

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[PATCH][SRU Bionic] PCI: Add decoding for 16 GT/s link speed

dann frazier-4
BugLink: https://bugs.launchpad.net/bugs/1773243

PCIe 4.0 defines the 16.0 GT/s link speed.  Links can run at that speed
without any Linux changes, but previously their sysfs "max_link_speed" and
"current_link_speed" files contained "Unknown speed", not the expected
"16.0 GT/s".

Add decoding for the new 16 GT/s link speed.

Signed-off-by: Jay Fang <[hidden email]>
[bhelgaas: add PCI_EXP_LNKCAP2_SLS_16_0GB]
Signed-off-by: Bjorn Helgaas <[hidden email]>
Reviewed-by: Dongdong Liu <[hidden email]>
(cherry picked from commit 1acfb9b7ee0b1881bb8e875b6757976e48293ec4)
Signed-off-by: dann frazier <[hidden email]>
---
 drivers/pci/pci-sysfs.c       | 6 ++++++
 drivers/pci/probe.c           | 2 +-
 drivers/pci/slot.c            | 1 +
 include/linux/pci.h           | 1 +
 include/uapi/linux/pci_regs.h | 7 +++++--
 5 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c
index b7b4486c2755..612e523551f8 100644
--- a/drivers/pci/pci-sysfs.c
+++ b/drivers/pci/pci-sysfs.c
@@ -168,6 +168,9 @@ static ssize_t max_link_speed_show(struct device *dev,
  return -EINVAL;
 
  switch (linkcap & PCI_EXP_LNKCAP_SLS) {
+ case PCI_EXP_LNKCAP_SLS_16_0GB:
+ speed = "16 GT/s";
+ break;
  case PCI_EXP_LNKCAP_SLS_8_0GB:
  speed = "8 GT/s";
  break;
@@ -213,6 +216,9 @@ static ssize_t current_link_speed_show(struct device *dev,
  return -EINVAL;
 
  switch (linkstat & PCI_EXP_LNKSTA_CLS) {
+ case PCI_EXP_LNKSTA_CLS_16_0GB:
+ speed = "16 GT/s";
+ break;
  case PCI_EXP_LNKSTA_CLS_8_0GB:
  speed = "8 GT/s";
  break;
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 070476036846..d0e7608dcb98 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -587,7 +587,7 @@ const unsigned char pcie_link_speed[] = {
  PCIE_SPEED_2_5GT, /* 1 */
  PCIE_SPEED_5_0GT, /* 2 */
  PCIE_SPEED_8_0GT, /* 3 */
- PCI_SPEED_UNKNOWN, /* 4 */
+ PCIE_SPEED_16_0GT, /* 4 */
  PCI_SPEED_UNKNOWN, /* 5 */
  PCI_SPEED_UNKNOWN, /* 6 */
  PCI_SPEED_UNKNOWN, /* 7 */
diff --git a/drivers/pci/slot.c b/drivers/pci/slot.c
index e42909524dee..7569e4e3a8a4 100644
--- a/drivers/pci/slot.c
+++ b/drivers/pci/slot.c
@@ -75,6 +75,7 @@ static const char *pci_bus_speed_strings[] = {
  "2.5 GT/s PCIe", /* 0x14 */
  "5.0 GT/s PCIe", /* 0x15 */
  "8.0 GT/s PCIe", /* 0x16 */
+ "16.0 GT/s PCIe", /* 0x17 */
 };
 
 static ssize_t bus_speed_read(enum pci_bus_speed speed, char *buf)
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 0962a3a36d62..5320e9757219 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -259,6 +259,7 @@ enum pci_bus_speed {
  PCIE_SPEED_2_5GT = 0x14,
  PCIE_SPEED_5_0GT = 0x15,
  PCIE_SPEED_8_0GT = 0x16,
+ PCIE_SPEED_16_0GT = 0x17,
  PCI_SPEED_UNKNOWN = 0xff,
 };
 
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index 70c2b2ade048..271f8f89f015 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -520,6 +520,7 @@
 #define  PCI_EXP_LNKCAP_SLS_2_5GB 0x00000001 /* LNKCAP2 SLS Vector bit 0 */
 #define  PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002 /* LNKCAP2 SLS Vector bit 1 */
 #define  PCI_EXP_LNKCAP_SLS_8_0GB 0x00000003 /* LNKCAP2 SLS Vector bit 2 */
+#define  PCI_EXP_LNKCAP_SLS_16_0GB 0x00000004 /* LNKCAP2 SLS Vector bit 3 */
 #define  PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */
 #define  PCI_EXP_LNKCAP_ASPMS 0x00000c00 /* ASPM Support */
 #define  PCI_EXP_LNKCAP_L0SEL 0x00007000 /* L0s Exit Latency */
@@ -547,6 +548,7 @@
 #define  PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 /* Current Link Speed 2.5GT/s */
 #define  PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */
 #define  PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */
+#define  PCI_EXP_LNKSTA_CLS_16_0GB 0x0004 /* Current Link Speed 16.0GT/s */
 #define  PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */
 #define  PCI_EXP_LNKSTA_NLW_X1 0x0010 /* Current Link Width x1 */
 #define  PCI_EXP_LNKSTA_NLW_X2 0x0020 /* Current Link Width x2 */
@@ -644,8 +646,9 @@
 #define PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V2 44 /* v2 endpoints without link end here */
 #define PCI_EXP_LNKCAP2 44 /* Link Capabilities 2 */
 #define  PCI_EXP_LNKCAP2_SLS_2_5GB 0x00000002 /* Supported Speed 2.5GT/s */
-#define  PCI_EXP_LNKCAP2_SLS_5_0GB 0x00000004 /* Supported Speed 5.0GT/s */
-#define  PCI_EXP_LNKCAP2_SLS_8_0GB 0x00000008 /* Supported Speed 8.0GT/s */
+#define  PCI_EXP_LNKCAP2_SLS_5_0GB 0x00000004 /* Supported Speed 5GT/s */
+#define  PCI_EXP_LNKCAP2_SLS_8_0GB 0x00000008 /* Supported Speed 8GT/s */
+#define  PCI_EXP_LNKCAP2_SLS_16_0GB 0x00000010 /* Supported Speed 16GT/s */
 #define  PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 /* Crosslink supported */
 #define PCI_EXP_LNKCTL2 48 /* Link Control 2 */
 #define PCI_EXP_LNKSTA2 50 /* Link Status 2 */
--
2.17.0


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ACK: [PATCH][SRU Bionic] PCI: Add decoding for 16 GT/s link speed

Kleber Souza
On 05/25/18 12:32, dann frazier wrote:

> BugLink: https://bugs.launchpad.net/bugs/1773243
>
> PCIe 4.0 defines the 16.0 GT/s link speed.  Links can run at that speed
> without any Linux changes, but previously their sysfs "max_link_speed" and
> "current_link_speed" files contained "Unknown speed", not the expected
> "16.0 GT/s".
>
> Add decoding for the new 16 GT/s link speed.
>
> Signed-off-by: Jay Fang <[hidden email]>
> [bhelgaas: add PCI_EXP_LNKCAP2_SLS_16_0GB]
> Signed-off-by: Bjorn Helgaas <[hidden email]>
> Reviewed-by: Dongdong Liu <[hidden email]>
> (cherry picked from commit 1acfb9b7ee0b1881bb8e875b6757976e48293ec4)
> Signed-off-by: dann frazier <[hidden email]>

Acked-by: Kleber Sacilotto de Souza <[hidden email]>

> ---
>  drivers/pci/pci-sysfs.c       | 6 ++++++
>  drivers/pci/probe.c           | 2 +-
>  drivers/pci/slot.c            | 1 +
>  include/linux/pci.h           | 1 +
>  include/uapi/linux/pci_regs.h | 7 +++++--
>  5 files changed, 14 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c
> index b7b4486c2755..612e523551f8 100644
> --- a/drivers/pci/pci-sysfs.c
> +++ b/drivers/pci/pci-sysfs.c
> @@ -168,6 +168,9 @@ static ssize_t max_link_speed_show(struct device *dev,
>   return -EINVAL;
>  
>   switch (linkcap & PCI_EXP_LNKCAP_SLS) {
> + case PCI_EXP_LNKCAP_SLS_16_0GB:
> + speed = "16 GT/s";
> + break;
>   case PCI_EXP_LNKCAP_SLS_8_0GB:
>   speed = "8 GT/s";
>   break;
> @@ -213,6 +216,9 @@ static ssize_t current_link_speed_show(struct device *dev,
>   return -EINVAL;
>  
>   switch (linkstat & PCI_EXP_LNKSTA_CLS) {
> + case PCI_EXP_LNKSTA_CLS_16_0GB:
> + speed = "16 GT/s";
> + break;
>   case PCI_EXP_LNKSTA_CLS_8_0GB:
>   speed = "8 GT/s";
>   break;
> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
> index 070476036846..d0e7608dcb98 100644
> --- a/drivers/pci/probe.c
> +++ b/drivers/pci/probe.c
> @@ -587,7 +587,7 @@ const unsigned char pcie_link_speed[] = {
>   PCIE_SPEED_2_5GT, /* 1 */
>   PCIE_SPEED_5_0GT, /* 2 */
>   PCIE_SPEED_8_0GT, /* 3 */
> - PCI_SPEED_UNKNOWN, /* 4 */
> + PCIE_SPEED_16_0GT, /* 4 */
>   PCI_SPEED_UNKNOWN, /* 5 */
>   PCI_SPEED_UNKNOWN, /* 6 */
>   PCI_SPEED_UNKNOWN, /* 7 */
> diff --git a/drivers/pci/slot.c b/drivers/pci/slot.c
> index e42909524dee..7569e4e3a8a4 100644
> --- a/drivers/pci/slot.c
> +++ b/drivers/pci/slot.c
> @@ -75,6 +75,7 @@ static const char *pci_bus_speed_strings[] = {
>   "2.5 GT/s PCIe", /* 0x14 */
>   "5.0 GT/s PCIe", /* 0x15 */
>   "8.0 GT/s PCIe", /* 0x16 */
> + "16.0 GT/s PCIe", /* 0x17 */
>  };
>  
>  static ssize_t bus_speed_read(enum pci_bus_speed speed, char *buf)
> diff --git a/include/linux/pci.h b/include/linux/pci.h
> index 0962a3a36d62..5320e9757219 100644
> --- a/include/linux/pci.h
> +++ b/include/linux/pci.h
> @@ -259,6 +259,7 @@ enum pci_bus_speed {
>   PCIE_SPEED_2_5GT = 0x14,
>   PCIE_SPEED_5_0GT = 0x15,
>   PCIE_SPEED_8_0GT = 0x16,
> + PCIE_SPEED_16_0GT = 0x17,
>   PCI_SPEED_UNKNOWN = 0xff,
>  };
>  
> diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
> index 70c2b2ade048..271f8f89f015 100644
> --- a/include/uapi/linux/pci_regs.h
> +++ b/include/uapi/linux/pci_regs.h
> @@ -520,6 +520,7 @@
>  #define  PCI_EXP_LNKCAP_SLS_2_5GB 0x00000001 /* LNKCAP2 SLS Vector bit 0 */
>  #define  PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002 /* LNKCAP2 SLS Vector bit 1 */
>  #define  PCI_EXP_LNKCAP_SLS_8_0GB 0x00000003 /* LNKCAP2 SLS Vector bit 2 */
> +#define  PCI_EXP_LNKCAP_SLS_16_0GB 0x00000004 /* LNKCAP2 SLS Vector bit 3 */
>  #define  PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */
>  #define  PCI_EXP_LNKCAP_ASPMS 0x00000c00 /* ASPM Support */
>  #define  PCI_EXP_LNKCAP_L0SEL 0x00007000 /* L0s Exit Latency */
> @@ -547,6 +548,7 @@
>  #define  PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 /* Current Link Speed 2.5GT/s */
>  #define  PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */
>  #define  PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */
> +#define  PCI_EXP_LNKSTA_CLS_16_0GB 0x0004 /* Current Link Speed 16.0GT/s */
>  #define  PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */
>  #define  PCI_EXP_LNKSTA_NLW_X1 0x0010 /* Current Link Width x1 */
>  #define  PCI_EXP_LNKSTA_NLW_X2 0x0020 /* Current Link Width x2 */
> @@ -644,8 +646,9 @@
>  #define PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V2 44 /* v2 endpoints without link end here */
>  #define PCI_EXP_LNKCAP2 44 /* Link Capabilities 2 */
>  #define  PCI_EXP_LNKCAP2_SLS_2_5GB 0x00000002 /* Supported Speed 2.5GT/s */
> -#define  PCI_EXP_LNKCAP2_SLS_5_0GB 0x00000004 /* Supported Speed 5.0GT/s */
> -#define  PCI_EXP_LNKCAP2_SLS_8_0GB 0x00000008 /* Supported Speed 8.0GT/s */
> +#define  PCI_EXP_LNKCAP2_SLS_5_0GB 0x00000004 /* Supported Speed 5GT/s */
> +#define  PCI_EXP_LNKCAP2_SLS_8_0GB 0x00000008 /* Supported Speed 8GT/s */
> +#define  PCI_EXP_LNKCAP2_SLS_16_0GB 0x00000010 /* Supported Speed 16GT/s */
>  #define  PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 /* Crosslink supported */
>  #define PCI_EXP_LNKCTL2 48 /* Link Control 2 */
>  #define PCI_EXP_LNKSTA2 50 /* Link Status 2 */
>

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ACK: [PATCH][SRU Bionic] PCI: Add decoding for 16 GT/s link speed

Khaled Elmously
In reply to this post by dann frazier-4
On 2018-05-25 13:32:16 , dann frazier wrote:

> BugLink: https://bugs.launchpad.net/bugs/1773243
>
> PCIe 4.0 defines the 16.0 GT/s link speed.  Links can run at that speed
> without any Linux changes, but previously their sysfs "max_link_speed" and
> "current_link_speed" files contained "Unknown speed", not the expected
> "16.0 GT/s".
>
> Add decoding for the new 16 GT/s link speed.
>
> Signed-off-by: Jay Fang <[hidden email]>
> [bhelgaas: add PCI_EXP_LNKCAP2_SLS_16_0GB]
> Signed-off-by: Bjorn Helgaas <[hidden email]>
> Reviewed-by: Dongdong Liu <[hidden email]>
> (cherry picked from commit 1acfb9b7ee0b1881bb8e875b6757976e48293ec4)
> Signed-off-by: dann frazier <[hidden email]>
> ---
>  drivers/pci/pci-sysfs.c       | 6 ++++++
>  drivers/pci/probe.c           | 2 +-
>  drivers/pci/slot.c            | 1 +
>  include/linux/pci.h           | 1 +
>  include/uapi/linux/pci_regs.h | 7 +++++--
>  5 files changed, 14 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c
> index b7b4486c2755..612e523551f8 100644
> --- a/drivers/pci/pci-sysfs.c
> +++ b/drivers/pci/pci-sysfs.c
> @@ -168,6 +168,9 @@ static ssize_t max_link_speed_show(struct device *dev,
>   return -EINVAL;
>  
>   switch (linkcap & PCI_EXP_LNKCAP_SLS) {
> + case PCI_EXP_LNKCAP_SLS_16_0GB:
> + speed = "16 GT/s";
> + break;
>   case PCI_EXP_LNKCAP_SLS_8_0GB:
>   speed = "8 GT/s";
>   break;
> @@ -213,6 +216,9 @@ static ssize_t current_link_speed_show(struct device *dev,
>   return -EINVAL;
>  
>   switch (linkstat & PCI_EXP_LNKSTA_CLS) {
> + case PCI_EXP_LNKSTA_CLS_16_0GB:
> + speed = "16 GT/s";
> + break;
>   case PCI_EXP_LNKSTA_CLS_8_0GB:
>   speed = "8 GT/s";
>   break;
> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
> index 070476036846..d0e7608dcb98 100644
> --- a/drivers/pci/probe.c
> +++ b/drivers/pci/probe.c
> @@ -587,7 +587,7 @@ const unsigned char pcie_link_speed[] = {
>   PCIE_SPEED_2_5GT, /* 1 */
>   PCIE_SPEED_5_0GT, /* 2 */
>   PCIE_SPEED_8_0GT, /* 3 */
> - PCI_SPEED_UNKNOWN, /* 4 */
> + PCIE_SPEED_16_0GT, /* 4 */
>   PCI_SPEED_UNKNOWN, /* 5 */
>   PCI_SPEED_UNKNOWN, /* 6 */
>   PCI_SPEED_UNKNOWN, /* 7 */
> diff --git a/drivers/pci/slot.c b/drivers/pci/slot.c
> index e42909524dee..7569e4e3a8a4 100644
> --- a/drivers/pci/slot.c
> +++ b/drivers/pci/slot.c
> @@ -75,6 +75,7 @@ static const char *pci_bus_speed_strings[] = {
>   "2.5 GT/s PCIe", /* 0x14 */
>   "5.0 GT/s PCIe", /* 0x15 */
>   "8.0 GT/s PCIe", /* 0x16 */
> + "16.0 GT/s PCIe", /* 0x17 */
>  };
>  
>  static ssize_t bus_speed_read(enum pci_bus_speed speed, char *buf)
> diff --git a/include/linux/pci.h b/include/linux/pci.h
> index 0962a3a36d62..5320e9757219 100644
> --- a/include/linux/pci.h
> +++ b/include/linux/pci.h
> @@ -259,6 +259,7 @@ enum pci_bus_speed {
>   PCIE_SPEED_2_5GT = 0x14,
>   PCIE_SPEED_5_0GT = 0x15,
>   PCIE_SPEED_8_0GT = 0x16,
> + PCIE_SPEED_16_0GT = 0x17,
>   PCI_SPEED_UNKNOWN = 0xff,
>  };
>  
> diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
> index 70c2b2ade048..271f8f89f015 100644
> --- a/include/uapi/linux/pci_regs.h
> +++ b/include/uapi/linux/pci_regs.h
> @@ -520,6 +520,7 @@
>  #define  PCI_EXP_LNKCAP_SLS_2_5GB 0x00000001 /* LNKCAP2 SLS Vector bit 0 */
>  #define  PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002 /* LNKCAP2 SLS Vector bit 1 */
>  #define  PCI_EXP_LNKCAP_SLS_8_0GB 0x00000003 /* LNKCAP2 SLS Vector bit 2 */
> +#define  PCI_EXP_LNKCAP_SLS_16_0GB 0x00000004 /* LNKCAP2 SLS Vector bit 3 */
>  #define  PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */
>  #define  PCI_EXP_LNKCAP_ASPMS 0x00000c00 /* ASPM Support */
>  #define  PCI_EXP_LNKCAP_L0SEL 0x00007000 /* L0s Exit Latency */
> @@ -547,6 +548,7 @@
>  #define  PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 /* Current Link Speed 2.5GT/s */
>  #define  PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */
>  #define  PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */
> +#define  PCI_EXP_LNKSTA_CLS_16_0GB 0x0004 /* Current Link Speed 16.0GT/s */
>  #define  PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */
>  #define  PCI_EXP_LNKSTA_NLW_X1 0x0010 /* Current Link Width x1 */
>  #define  PCI_EXP_LNKSTA_NLW_X2 0x0020 /* Current Link Width x2 */
> @@ -644,8 +646,9 @@
>  #define PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V2 44 /* v2 endpoints without link end here */
>  #define PCI_EXP_LNKCAP2 44 /* Link Capabilities 2 */
>  #define  PCI_EXP_LNKCAP2_SLS_2_5GB 0x00000002 /* Supported Speed 2.5GT/s */
> -#define  PCI_EXP_LNKCAP2_SLS_5_0GB 0x00000004 /* Supported Speed 5.0GT/s */
> -#define  PCI_EXP_LNKCAP2_SLS_8_0GB 0x00000008 /* Supported Speed 8.0GT/s */
> +#define  PCI_EXP_LNKCAP2_SLS_5_0GB 0x00000004 /* Supported Speed 5GT/s */
> +#define  PCI_EXP_LNKCAP2_SLS_8_0GB 0x00000008 /* Supported Speed 8GT/s */
> +#define  PCI_EXP_LNKCAP2_SLS_16_0GB 0x00000010 /* Supported Speed 16GT/s */
>  #define  PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 /* Crosslink supported */
>  #define PCI_EXP_LNKCTL2 48 /* Link Control 2 */
>  #define PCI_EXP_LNKSTA2 50 /* Link Status 2 */

Acked-by: Khalid Elmously <[hidden email]>


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APPLIED: [PATCH][SRU Bionic] PCI: Add decoding for 16 GT/s link speed

Khaled Elmously
In reply to this post by dann frazier-4
Applied to Bionic

On 2018-05-25 13:32:16 , dann frazier wrote:

> BugLink: https://bugs.launchpad.net/bugs/1773243
>
> PCIe 4.0 defines the 16.0 GT/s link speed.  Links can run at that speed
> without any Linux changes, but previously their sysfs "max_link_speed" and
> "current_link_speed" files contained "Unknown speed", not the expected
> "16.0 GT/s".
>
> Add decoding for the new 16 GT/s link speed.
>
> Signed-off-by: Jay Fang <[hidden email]>
> [bhelgaas: add PCI_EXP_LNKCAP2_SLS_16_0GB]
> Signed-off-by: Bjorn Helgaas <[hidden email]>
> Reviewed-by: Dongdong Liu <[hidden email]>
> (cherry picked from commit 1acfb9b7ee0b1881bb8e875b6757976e48293ec4)
> Signed-off-by: dann frazier <[hidden email]>
> ---
>  drivers/pci/pci-sysfs.c       | 6 ++++++
>  drivers/pci/probe.c           | 2 +-
>  drivers/pci/slot.c            | 1 +
>  include/linux/pci.h           | 1 +
>  include/uapi/linux/pci_regs.h | 7 +++++--
>  5 files changed, 14 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c
> index b7b4486c2755..612e523551f8 100644
> --- a/drivers/pci/pci-sysfs.c
> +++ b/drivers/pci/pci-sysfs.c
> @@ -168,6 +168,9 @@ static ssize_t max_link_speed_show(struct device *dev,
>   return -EINVAL;
>  
>   switch (linkcap & PCI_EXP_LNKCAP_SLS) {
> + case PCI_EXP_LNKCAP_SLS_16_0GB:
> + speed = "16 GT/s";
> + break;
>   case PCI_EXP_LNKCAP_SLS_8_0GB:
>   speed = "8 GT/s";
>   break;
> @@ -213,6 +216,9 @@ static ssize_t current_link_speed_show(struct device *dev,
>   return -EINVAL;
>  
>   switch (linkstat & PCI_EXP_LNKSTA_CLS) {
> + case PCI_EXP_LNKSTA_CLS_16_0GB:
> + speed = "16 GT/s";
> + break;
>   case PCI_EXP_LNKSTA_CLS_8_0GB:
>   speed = "8 GT/s";
>   break;
> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
> index 070476036846..d0e7608dcb98 100644
> --- a/drivers/pci/probe.c
> +++ b/drivers/pci/probe.c
> @@ -587,7 +587,7 @@ const unsigned char pcie_link_speed[] = {
>   PCIE_SPEED_2_5GT, /* 1 */
>   PCIE_SPEED_5_0GT, /* 2 */
>   PCIE_SPEED_8_0GT, /* 3 */
> - PCI_SPEED_UNKNOWN, /* 4 */
> + PCIE_SPEED_16_0GT, /* 4 */
>   PCI_SPEED_UNKNOWN, /* 5 */
>   PCI_SPEED_UNKNOWN, /* 6 */
>   PCI_SPEED_UNKNOWN, /* 7 */
> diff --git a/drivers/pci/slot.c b/drivers/pci/slot.c
> index e42909524dee..7569e4e3a8a4 100644
> --- a/drivers/pci/slot.c
> +++ b/drivers/pci/slot.c
> @@ -75,6 +75,7 @@ static const char *pci_bus_speed_strings[] = {
>   "2.5 GT/s PCIe", /* 0x14 */
>   "5.0 GT/s PCIe", /* 0x15 */
>   "8.0 GT/s PCIe", /* 0x16 */
> + "16.0 GT/s PCIe", /* 0x17 */
>  };
>  
>  static ssize_t bus_speed_read(enum pci_bus_speed speed, char *buf)
> diff --git a/include/linux/pci.h b/include/linux/pci.h
> index 0962a3a36d62..5320e9757219 100644
> --- a/include/linux/pci.h
> +++ b/include/linux/pci.h
> @@ -259,6 +259,7 @@ enum pci_bus_speed {
>   PCIE_SPEED_2_5GT = 0x14,
>   PCIE_SPEED_5_0GT = 0x15,
>   PCIE_SPEED_8_0GT = 0x16,
> + PCIE_SPEED_16_0GT = 0x17,
>   PCI_SPEED_UNKNOWN = 0xff,
>  };
>  
> diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
> index 70c2b2ade048..271f8f89f015 100644
> --- a/include/uapi/linux/pci_regs.h
> +++ b/include/uapi/linux/pci_regs.h
> @@ -520,6 +520,7 @@
>  #define  PCI_EXP_LNKCAP_SLS_2_5GB 0x00000001 /* LNKCAP2 SLS Vector bit 0 */
>  #define  PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002 /* LNKCAP2 SLS Vector bit 1 */
>  #define  PCI_EXP_LNKCAP_SLS_8_0GB 0x00000003 /* LNKCAP2 SLS Vector bit 2 */
> +#define  PCI_EXP_LNKCAP_SLS_16_0GB 0x00000004 /* LNKCAP2 SLS Vector bit 3 */
>  #define  PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */
>  #define  PCI_EXP_LNKCAP_ASPMS 0x00000c00 /* ASPM Support */
>  #define  PCI_EXP_LNKCAP_L0SEL 0x00007000 /* L0s Exit Latency */
> @@ -547,6 +548,7 @@
>  #define  PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 /* Current Link Speed 2.5GT/s */
>  #define  PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */
>  #define  PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */
> +#define  PCI_EXP_LNKSTA_CLS_16_0GB 0x0004 /* Current Link Speed 16.0GT/s */
>  #define  PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */
>  #define  PCI_EXP_LNKSTA_NLW_X1 0x0010 /* Current Link Width x1 */
>  #define  PCI_EXP_LNKSTA_NLW_X2 0x0020 /* Current Link Width x2 */
> @@ -644,8 +646,9 @@
>  #define PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V2 44 /* v2 endpoints without link end here */
>  #define PCI_EXP_LNKCAP2 44 /* Link Capabilities 2 */
>  #define  PCI_EXP_LNKCAP2_SLS_2_5GB 0x00000002 /* Supported Speed 2.5GT/s */
> -#define  PCI_EXP_LNKCAP2_SLS_5_0GB 0x00000004 /* Supported Speed 5.0GT/s */
> -#define  PCI_EXP_LNKCAP2_SLS_8_0GB 0x00000008 /* Supported Speed 8.0GT/s */
> +#define  PCI_EXP_LNKCAP2_SLS_5_0GB 0x00000004 /* Supported Speed 5GT/s */
> +#define  PCI_EXP_LNKCAP2_SLS_8_0GB 0x00000008 /* Supported Speed 8GT/s */
> +#define  PCI_EXP_LNKCAP2_SLS_16_0GB 0x00000010 /* Supported Speed 16GT/s */
>  #define  PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 /* Crosslink supported */
>  #define PCI_EXP_LNKCTL2 48 /* Link Control 2 */
>  #define PCI_EXP_LNKSTA2 50 /* Link Status 2 */
> --
> 2.17.0
>
>
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