[PATCH] kvm: nVMX: Don't allow L2 to access the hardware CR8

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[PATCH] kvm: nVMX: Don't allow L2 to access the hardware CR8

Stefan Bader-2
From: Jim Mattson <[hidden email]>

If L1 does not specify the "use TPR shadow" VM-execution control in
vmcs12, then L0 must specify the "CR8-load exiting" and "CR8-store
exiting" VM-execution controls in vmcs02. Failure to do so will give
the L2 VM unrestricted read/write access to the hardware CR8.

This fixes CVE-2017-12154.

Signed-off-by: Jim Mattson <[hidden email]>
Reviewed-by: David Hildenbrand <[hidden email]>
Signed-off-by: Paolo Bonzini <[hidden email]>

CVE-2017-12154

(backported from commit 51aa68e7d57e3217192d88ce90fd5b8ef29ec94f)
Signed-off-by: Stefan Bader <[hidden email]>
---
 arch/x86/kvm/vmx.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index 45af82c..6f2d4493 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -7837,6 +7837,14 @@ static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
  exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
  exec_control &= ~CPU_BASED_TPR_SHADOW;
  exec_control |= vmcs12->cpu_based_vm_exec_control;
+
+ if (!(exec_control & CPU_BASED_TPR_SHADOW)) {
+#ifdef CONFIG_X86_64
+ exec_control |= CPU_BASED_CR8_LOAD_EXITING |
+ CPU_BASED_CR8_STORE_EXITING;
+#endif
+ }
+
  /*
  * Merging of IO and MSR bitmaps not currently supported.
  * Rather, exit every time.
--
2.7.4


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Re: [SRU Trusty] kvm: nVMX: Don't allow L2 to access the hardware CR8

Stefan Bader-2
On 06.06.2018 15:22, Stefan Bader wrote:

> From: Jim Mattson <[hidden email]>
>
> If L1 does not specify the "use TPR shadow" VM-execution control in
> vmcs12, then L0 must specify the "CR8-load exiting" and "CR8-store
> exiting" VM-execution controls in vmcs02. Failure to do so will give
> the L2 VM unrestricted read/write access to the hardware CR8.
>
> This fixes CVE-2017-12154.
>
> Signed-off-by: Jim Mattson <[hidden email]>
> Reviewed-by: David Hildenbrand <[hidden email]>
> Signed-off-by: Paolo Bonzini <[hidden email]>
>
> CVE-2017-12154
>
> (backported from commit 51aa68e7d57e3217192d88ce90fd5b8ef29ec94f)
> Signed-off-by: Stefan Bader <[hidden email]>
> ---
Messed up the destination, sorry.

>  arch/x86/kvm/vmx.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
>
> diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
> index 45af82c..6f2d4493 100644
> --- a/arch/x86/kvm/vmx.c
> +++ b/arch/x86/kvm/vmx.c
> @@ -7837,6 +7837,14 @@ static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
>   exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
>   exec_control &= ~CPU_BASED_TPR_SHADOW;
>   exec_control |= vmcs12->cpu_based_vm_exec_control;
> +
> + if (!(exec_control & CPU_BASED_TPR_SHADOW)) {
> +#ifdef CONFIG_X86_64
> + exec_control |= CPU_BASED_CR8_LOAD_EXITING |
> + CPU_BASED_CR8_STORE_EXITING;
> +#endif
> + }
> +
>   /*
>   * Merging of IO and MSR bitmaps not currently supported.
>   * Rather, exit every time.
>


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ACK[Trusty]: [PATCH] kvm: nVMX: Don't allow L2 to access the hardware CR8

Kleber Sacilotto de Souza
In reply to this post by Stefan Bader-2
On 06/06/18 15:22, Stefan Bader wrote:

> From: Jim Mattson <[hidden email]>
>
> If L1 does not specify the "use TPR shadow" VM-execution control in
> vmcs12, then L0 must specify the "CR8-load exiting" and "CR8-store
> exiting" VM-execution controls in vmcs02. Failure to do so will give
> the L2 VM unrestricted read/write access to the hardware CR8.
>
> This fixes CVE-2017-12154.
>
> Signed-off-by: Jim Mattson <[hidden email]>
> Reviewed-by: David Hildenbrand <[hidden email]>
> Signed-off-by: Paolo Bonzini <[hidden email]>
>
> CVE-2017-12154
>
> (backported from commit 51aa68e7d57e3217192d88ce90fd5b8ef29ec94f)
> Signed-off-by: Stefan Bader <[hidden email]>
> ---
>  arch/x86/kvm/vmx.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
>
> diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
> index 45af82c..6f2d4493 100644
> --- a/arch/x86/kvm/vmx.c
> +++ b/arch/x86/kvm/vmx.c
> @@ -7837,6 +7837,14 @@ static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
>   exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
>   exec_control &= ~CPU_BASED_TPR_SHADOW;
>   exec_control |= vmcs12->cpu_based_vm_exec_control;
> +
> + if (!(exec_control & CPU_BASED_TPR_SHADOW)) {
> +#ifdef CONFIG_X86_64
> + exec_control |= CPU_BASED_CR8_LOAD_EXITING |
> + CPU_BASED_CR8_STORE_EXITING;
> +#endif
> + }
> +
>   /*
>   * Merging of IO and MSR bitmaps not currently supported.
>   * Rather, exit every time.
>

The backport looks correct.

Acked-by: Kleber Sacilotto de Souza <[hidden email]>

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ACK: [PATCH] kvm: nVMX: Don't allow L2 to access the hardware CR8

Khaled Elmously
In reply to this post by Stefan Bader-2
On 2018-06-06 15:22:39 , Stefan Bader wrote:

> From: Jim Mattson <[hidden email]>
>
> If L1 does not specify the "use TPR shadow" VM-execution control in
> vmcs12, then L0 must specify the "CR8-load exiting" and "CR8-store
> exiting" VM-execution controls in vmcs02. Failure to do so will give
> the L2 VM unrestricted read/write access to the hardware CR8.
>
> This fixes CVE-2017-12154.
>
> Signed-off-by: Jim Mattson <[hidden email]>
> Reviewed-by: David Hildenbrand <[hidden email]>
> Signed-off-by: Paolo Bonzini <[hidden email]>
>
> CVE-2017-12154
>
> (backported from commit 51aa68e7d57e3217192d88ce90fd5b8ef29ec94f)
> Signed-off-by: Stefan Bader <[hidden email]>
> ---
>  arch/x86/kvm/vmx.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
>
> diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
> index 45af82c..6f2d4493 100644
> --- a/arch/x86/kvm/vmx.c
> +++ b/arch/x86/kvm/vmx.c
> @@ -7837,6 +7837,14 @@ static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
>   exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
>   exec_control &= ~CPU_BASED_TPR_SHADOW;
>   exec_control |= vmcs12->cpu_based_vm_exec_control;
> +
> + if (!(exec_control & CPU_BASED_TPR_SHADOW)) {
> +#ifdef CONFIG_X86_64
> + exec_control |= CPU_BASED_CR8_LOAD_EXITING |
> + CPU_BASED_CR8_STORE_EXITING;
> +#endif
> + }
> +
>   /*
>   * Merging of IO and MSR bitmaps not currently supported.
>   * Rather, exit every time.

Acked-by: Khalid Elmously <[hidden email]>


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APPLIED[T]: [PATCH] kvm: nVMX: Don't allow L2 to access the hardware CR8

Khaled Elmously
In reply to this post by Stefan Bader-2
Applied to Trusty

On 2018-06-06 15:22:39 , Stefan Bader wrote:

> From: Jim Mattson <[hidden email]>
>
> If L1 does not specify the "use TPR shadow" VM-execution control in
> vmcs12, then L0 must specify the "CR8-load exiting" and "CR8-store
> exiting" VM-execution controls in vmcs02. Failure to do so will give
> the L2 VM unrestricted read/write access to the hardware CR8.
>
> This fixes CVE-2017-12154.
>
> Signed-off-by: Jim Mattson <[hidden email]>
> Reviewed-by: David Hildenbrand <[hidden email]>
> Signed-off-by: Paolo Bonzini <[hidden email]>
>
> CVE-2017-12154
>
> (backported from commit 51aa68e7d57e3217192d88ce90fd5b8ef29ec94f)
> Signed-off-by: Stefan Bader <[hidden email]>
> ---
>  arch/x86/kvm/vmx.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
>
> diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
> index 45af82c..6f2d4493 100644
> --- a/arch/x86/kvm/vmx.c
> +++ b/arch/x86/kvm/vmx.c
> @@ -7837,6 +7837,14 @@ static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
>   exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
>   exec_control &= ~CPU_BASED_TPR_SHADOW;
>   exec_control |= vmcs12->cpu_based_vm_exec_control;
> +
> + if (!(exec_control & CPU_BASED_TPR_SHADOW)) {
> +#ifdef CONFIG_X86_64
> + exec_control |= CPU_BASED_CR8_LOAD_EXITING |
> + CPU_BASED_CR8_STORE_EXITING;
> +#endif
> + }
> +
>   /*
>   * Merging of IO and MSR bitmaps not currently supported.
>   * Rather, exit every time.
> --
> 2.7.4
>
>
> --
> kernel-team mailing list
> [hidden email]
> https://lists.ubuntu.com/mailman/listinfo/kernel-team

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