[SRU] [B/C/D/Unstable/OEM-B] [PATCH 0/1] Workaround CSS timeout on AMD SNPS 3.0 xHC

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[SRU] [B/C/D/Unstable/OEM-B] [PATCH 0/1] Workaround CSS timeout on AMD SNPS 3.0 xHC

Kai-Heng Feng
BugLink: https://bugs.launchpad.net/bugs/1806838

[Impact]
Raven Ridge xHC may fail to suspend, causes the USB stops working, and
blocks the system entering system-wide suspend.

[Fix]
It's a hardware/firmware bug, workarounded by bailing out suspend
function if it ever fails, and reset the xHC in next resume function.

[Test]
After applying the patch, the USB works, and the system can enter S3
consecutively.

[Regression Potential]
Minimal. This workaround only applies to AMD Raven Ridge xHC.

Sandeep Singh (1):
  xhci: workaround CSS timeout on AMD SNPS 3.0 xHC

 drivers/usb/host/xhci-pci.c |  4 ++++
 drivers/usb/host/xhci.c     | 26 ++++++++++++++++++++++----
 drivers/usb/host/xhci.h     |  3 +++
 3 files changed, 29 insertions(+), 4 deletions(-)

--
2.17.1


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[Bionic] [PATCH 1/2] xhci: Allow more than 32 quirks

Kai-Heng Feng
From: Marc Zyngier <[hidden email]>

BugLink: https://bugs.launchpad.net/bugs/1806838

We now have 32 different quirks, and the field that holds them
is full. Let's bump it up to the next stage so that we can handle
some more... The type is now an unsigned long long, which is 64bit
on most architectures.

We take this opportunity to change the quirks from using (1 << x)
to BIT_ULL(x).

Tested-by: Domenico Andreoli <[hidden email]>
Signed-off-by: Marc Zyngier <[hidden email]>
Tested-by: Faiz Abbas <[hidden email]>
Tested-by: Domenico Andreoli <[hidden email]>
Acked-by: Mathias Nyman <[hidden email]>
Signed-off-by: Greg Kroah-Hartman <[hidden email]>
(backported from commit 36b6857932f380fcb55c31ac75857e3e81dd583a)
Signed-off-by: Kai-Heng Feng <[hidden email]>
---
 drivers/usb/host/xhci.c |  6 ++--
 drivers/usb/host/xhci.h | 64 ++++++++++++++++++++---------------------
 2 files changed, 35 insertions(+), 35 deletions(-)

diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index 16cb66599f72..2ad8d16811f5 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -33,8 +33,8 @@ static int link_quirk;
 module_param(link_quirk, int, S_IRUGO | S_IWUSR);
 MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
 
-static unsigned int quirks;
-module_param(quirks, uint, S_IRUGO);
+static unsigned long long quirks;
+module_param(quirks, ullong, S_IRUGO);
 MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default");
 
 /* TODO: copied from ehci-hcd.c - can this be refactored? */
@@ -4907,7 +4907,7 @@ int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
  return retval;
  xhci_dbg(xhci, "Called HCD init\n");
 
- xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%08x\n",
+ xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%016llx\n",
   xhci->hcc_params, xhci->hci_version, xhci->quirks);
 
  return 0;
diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
index 1703473aad7a..b80767aeedeb 100644
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
@@ -1782,12 +1782,12 @@ struct xhci_hcd {
 #define XHCI_STATE_DYING (1 << 0)
 #define XHCI_STATE_HALTED (1 << 1)
 #define XHCI_STATE_REMOVING (1 << 2)
- unsigned int quirks;
-#define XHCI_LINK_TRB_QUIRK (1 << 0)
-#define XHCI_RESET_EP_QUIRK (1 << 1)
-#define XHCI_NEC_HOST (1 << 2)
-#define XHCI_AMD_PLL_FIX (1 << 3)
-#define XHCI_SPURIOUS_SUCCESS (1 << 4)
+ unsigned long long quirks;
+#define XHCI_LINK_TRB_QUIRK BIT_ULL(0)
+#define XHCI_RESET_EP_QUIRK BIT_ULL(1)
+#define XHCI_NEC_HOST BIT_ULL(2)
+#define XHCI_AMD_PLL_FIX BIT_ULL(3)
+#define XHCI_SPURIOUS_SUCCESS BIT_ULL(4)
 /*
  * Certain Intel host controllers have a limit to the number of endpoint
  * contexts they can handle.  Ideally, they would signal that they can't handle
@@ -1797,34 +1797,34 @@ struct xhci_hcd {
  * commands, reset device commands, disable slot commands, and address device
  * commands.
  */
-#define XHCI_EP_LIMIT_QUIRK (1 << 5)
-#define XHCI_BROKEN_MSI (1 << 6)
-#define XHCI_RESET_ON_RESUME (1 << 7)
-#define XHCI_SW_BW_CHECKING (1 << 8)
-#define XHCI_AMD_0x96_HOST (1 << 9)
-#define XHCI_TRUST_TX_LENGTH (1 << 10)
-#define XHCI_LPM_SUPPORT (1 << 11)
-#define XHCI_INTEL_HOST (1 << 12)
-#define XHCI_SPURIOUS_REBOOT (1 << 13)
-#define XHCI_COMP_MODE_QUIRK (1 << 14)
-#define XHCI_AVOID_BEI (1 << 15)
-#define XHCI_PLAT (1 << 16)
-#define XHCI_SLOW_SUSPEND (1 << 17)
-#define XHCI_SPURIOUS_WAKEUP (1 << 18)
+#define XHCI_EP_LIMIT_QUIRK BIT_ULL(5)
+#define XHCI_BROKEN_MSI BIT_ULL(6)
+#define XHCI_RESET_ON_RESUME BIT_ULL(7)
+#define XHCI_SW_BW_CHECKING BIT_ULL(8)
+#define XHCI_AMD_0x96_HOST BIT_ULL(9)
+#define XHCI_TRUST_TX_LENGTH BIT_ULL(10)
+#define XHCI_LPM_SUPPORT BIT_ULL(11)
+#define XHCI_INTEL_HOST BIT_ULL(12)
+#define XHCI_SPURIOUS_REBOOT BIT_ULL(13)
+#define XHCI_COMP_MODE_QUIRK BIT_ULL(14)
+#define XHCI_AVOID_BEI BIT_ULL(15)
+#define XHCI_PLAT BIT_ULL(16)
+#define XHCI_SLOW_SUSPEND BIT_ULL(17)
+#define XHCI_SPURIOUS_WAKEUP BIT_ULL(18)
 /* For controllers with a broken beyond repair streams implementation */
-#define XHCI_BROKEN_STREAMS (1 << 19)
-#define XHCI_PME_STUCK_QUIRK (1 << 20)
-#define XHCI_MTK_HOST (1 << 21)
-#define XHCI_SSIC_PORT_UNUSED (1 << 22)
-#define XHCI_NO_64BIT_SUPPORT (1 << 23)
-#define XHCI_MISSING_CAS (1 << 24)
+#define XHCI_BROKEN_STREAMS BIT_ULL(19)
+#define XHCI_PME_STUCK_QUIRK BIT_ULL(20)
+#define XHCI_MTK_HOST BIT_ULL(21)
+#define XHCI_SSIC_PORT_UNUSED BIT_ULL(22)
+#define XHCI_NO_64BIT_SUPPORT BIT_ULL(23)
+#define XHCI_MISSING_CAS BIT_ULL(24)
 /* For controller with a broken Port Disable implementation */
-#define XHCI_BROKEN_PORT_PED (1 << 25)
-#define XHCI_LIMIT_ENDPOINT_INTERVAL_7 (1 << 26)
-#define XHCI_U2_DISABLE_WAKE (1 << 27)
-#define XHCI_ASMEDIA_MODIFY_FLOWCONTROL (1 << 28)
-#define XHCI_HW_LPM_DISABLE (1 << 29)
-#define XHCI_SUSPEND_DELAY (1 << 30)
+#define XHCI_BROKEN_PORT_PED BIT_ULL(25)
+#define XHCI_LIMIT_ENDPOINT_INTERVAL_7 BIT_ULL(26)
+#define XHCI_U2_DISABLE_WAKE BIT_ULL(27)
+#define XHCI_ASMEDIA_MODIFY_FLOWCONTROL BIT_ULL(28)
+#define XHCI_HW_LPM_DISABLE BIT_ULL(29)
+#define XHCI_SUSPEND_DELAY BIT_ULL(30)
 
  unsigned int num_active_eps;
  unsigned int limit_active_eps;
--
2.17.1


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[Bionic] [PATCH 2/2] xhci: workaround CSS timeout on AMD SNPS 3.0 xHC

Kai-Heng Feng
In reply to this post by Kai-Heng Feng
From: Sandeep Singh <[hidden email]>

BugLink: https://bugs.launchpad.net/bugs/1806838

Occasionally AMD SNPS 3.0 xHC does not respond to
CSS when set, also it does not flag anything on SRE and HCE
to point the internal xHC errors on USBSTS register. This stalls
the entire system wide suspend and there is no point in stalling
just because of xHC CSS is not responding.

To work around this problem, if the xHC does not flag
anything on SRE and HCE, we can skip the CSS
timeout and allow the system to continue the suspend. Once the
system resume happens we can internally reset the controller
using XHCI_RESET_ON_RESUME quirk

Signed-off-by: Shyam Sundar S K <[hidden email]>
Signed-off-by: Sandeep Singh <[hidden email]>
cc: Nehal Shah <[hidden email]>
Cc: <[hidden email]>
Tested-by: Kai-Heng Feng <[hidden email]>
Signed-off-by: Mathias Nyman <[hidden email]>
(backported from commit b5282b66f0dfe6e76644c5195ec6aa3de15fefa3 git://git.kernel.org/pub/scm/linux/kernel/git/mnyman/xhci.git for-usb-linus)
Signed-off-by: Kai-Heng Feng <[hidden email]>
---
 drivers/usb/host/xhci-pci.c |  4 ++++
 drivers/usb/host/xhci.c     | 26 ++++++++++++++++++++++----
 drivers/usb/host/xhci.h     |  3 +++
 3 files changed, 29 insertions(+), 4 deletions(-)

diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c
index c3ae5784649a..c62fa1424601 100644
--- a/drivers/usb/host/xhci-pci.c
+++ b/drivers/usb/host/xhci-pci.c
@@ -132,6 +132,10 @@ static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
  pdev->device == 0x43bb))
  xhci->quirks |= XHCI_SUSPEND_DELAY;
 
+ if (pdev->vendor == PCI_VENDOR_ID_AMD &&
+    (pdev->device == 0x15e0 || pdev->device == 0x15e1))
+ xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND;
+
  if (pdev->vendor == PCI_VENDOR_ID_AMD)
  xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 
diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index 2ad8d16811f5..c700bfb809df 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -866,6 +866,7 @@ int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
  unsigned int delay = XHCI_MAX_HALT_USEC;
  struct usb_hcd *hcd = xhci_to_hcd(xhci);
  u32 command;
+ u32 res;
 
  if (!hcd->state)
  return 0;
@@ -919,11 +920,28 @@ int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
  command = readl(&xhci->op_regs->command);
  command |= CMD_CSS;
  writel(command, &xhci->op_regs->command);
+ xhci->broken_suspend = 0;
  if (xhci_handshake(&xhci->op_regs->status,
  STS_SAVE, 0, 10 * 1000)) {
- xhci_warn(xhci, "WARN: xHC save state timeout\n");
- spin_unlock_irq(&xhci->lock);
- return -ETIMEDOUT;
+ /*
+ * AMD SNPS xHC 3.0 occasionally does not clear the
+ * SSS bit of USBSTS and when driver tries to poll
+ * to see if the xHC clears BIT(8) which never happens
+ * and driver assumes that controller is not responding
+ * and times out. To workaround this, its good to check
+ * if SRE and HCE bits are not set (as per xhci
+ * Section 5.4.2) and bypass the timeout.
+ */
+ res = readl(&xhci->op_regs->status);
+ if ((xhci->quirks & XHCI_SNPS_BROKEN_SUSPEND) &&
+    (((res & STS_SRE) == 0) &&
+ ((res & STS_HCE) == 0))) {
+ xhci->broken_suspend = 1;
+ } else {
+ xhci_warn(xhci, "WARN: xHC save state timeout\n");
+ spin_unlock_irq(&xhci->lock);
+ return -ETIMEDOUT;
+ }
  }
  spin_unlock_irq(&xhci->lock);
 
@@ -976,7 +994,7 @@ int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
  set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
 
  spin_lock_irq(&xhci->lock);
- if (xhci->quirks & XHCI_RESET_ON_RESUME)
+ if ((xhci->quirks & XHCI_RESET_ON_RESUME) || xhci->broken_suspend)
  hibernated = true;
 
  if (!hibernated) {
diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
index b80767aeedeb..269b2f4a9039 100644
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
@@ -1825,6 +1825,7 @@ struct xhci_hcd {
 #define XHCI_ASMEDIA_MODIFY_FLOWCONTROL BIT_ULL(28)
 #define XHCI_HW_LPM_DISABLE BIT_ULL(29)
 #define XHCI_SUSPEND_DELAY BIT_ULL(30)
+#define XHCI_SNPS_BROKEN_SUSPEND    BIT_ULL(35)
 
  unsigned int num_active_eps;
  unsigned int limit_active_eps;
@@ -1861,6 +1862,8 @@ struct xhci_hcd {
  void *dbc;
  /* platform-specific data -- must come last */
  unsigned long priv[0] __aligned(sizeof(s64));
+ /* Broken Suspend flag for SNPS Suspend resume issue */
+ u8 broken_suspend;
 };
 
 /* Platform specific overrides to generic XHCI hc_driver ops */
--
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[C/D/Unstable] [PATCH 1/1] xhci: workaround CSS timeout on AMD SNPS 3.0 xHC

Kai-Heng Feng
In reply to this post by Kai-Heng Feng
From: Sandeep Singh <[hidden email]>

BugLink: https://bugs.launchpad.net/bugs/1806838

Occasionally AMD SNPS 3.0 xHC does not respond to
CSS when set, also it does not flag anything on SRE and HCE
to point the internal xHC errors on USBSTS register. This stalls
the entire system wide suspend and there is no point in stalling
just because of xHC CSS is not responding.

To work around this problem, if the xHC does not flag
anything on SRE and HCE, we can skip the CSS
timeout and allow the system to continue the suspend. Once the
system resume happens we can internally reset the controller
using XHCI_RESET_ON_RESUME quirk

Signed-off-by: Shyam Sundar S K <[hidden email]>
Signed-off-by: Sandeep Singh <[hidden email]>
cc: Nehal Shah <[hidden email]>
Cc: <[hidden email]>
Tested-by: Kai-Heng Feng <[hidden email]>
Signed-off-by: Mathias Nyman <[hidden email]>
(backported from commit b5282b66f0dfe6e76644c5195ec6aa3de15fefa3 git://git.kernel.org/pub/scm/linux/kernel/git/mnyman/xhci.git for-usb-linus)
Signed-off-by: Kai-Heng Feng <[hidden email]>
---
 drivers/usb/host/xhci-pci.c |  4 ++++
 drivers/usb/host/xhci.c     | 26 ++++++++++++++++++++++----
 drivers/usb/host/xhci.h     |  3 +++
 3 files changed, 29 insertions(+), 4 deletions(-)

diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c
index 51dd8e00c4f8..921b4b41d760 100644
--- a/drivers/usb/host/xhci-pci.c
+++ b/drivers/usb/host/xhci-pci.c
@@ -132,6 +132,10 @@ static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
  pdev->device == 0x43bb))
  xhci->quirks |= XHCI_SUSPEND_DELAY;
 
+ if (pdev->vendor == PCI_VENDOR_ID_AMD &&
+    (pdev->device == 0x15e0 || pdev->device == 0x15e1))
+ xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND;
+
  if (pdev->vendor == PCI_VENDOR_ID_AMD)
  xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 
diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index 0420eefa647a..808677db1335 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -970,6 +970,7 @@ int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
  unsigned int delay = XHCI_MAX_HALT_USEC;
  struct usb_hcd *hcd = xhci_to_hcd(xhci);
  u32 command;
+ u32 res;
 
  if (!hcd->state)
  return 0;
@@ -1023,11 +1024,28 @@ int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
  command = readl(&xhci->op_regs->command);
  command |= CMD_CSS;
  writel(command, &xhci->op_regs->command);
+ xhci->broken_suspend = 0;
  if (xhci_handshake(&xhci->op_regs->status,
  STS_SAVE, 0, 10 * 1000)) {
- xhci_warn(xhci, "WARN: xHC save state timeout\n");
- spin_unlock_irq(&xhci->lock);
- return -ETIMEDOUT;
+ /*
+ * AMD SNPS xHC 3.0 occasionally does not clear the
+ * SSS bit of USBSTS and when driver tries to poll
+ * to see if the xHC clears BIT(8) which never happens
+ * and driver assumes that controller is not responding
+ * and times out. To workaround this, its good to check
+ * if SRE and HCE bits are not set (as per xhci
+ * Section 5.4.2) and bypass the timeout.
+ */
+ res = readl(&xhci->op_regs->status);
+ if ((xhci->quirks & XHCI_SNPS_BROKEN_SUSPEND) &&
+    (((res & STS_SRE) == 0) &&
+ ((res & STS_HCE) == 0))) {
+ xhci->broken_suspend = 1;
+ } else {
+ xhci_warn(xhci, "WARN: xHC save state timeout\n");
+ spin_unlock_irq(&xhci->lock);
+ return -ETIMEDOUT;
+ }
  }
  spin_unlock_irq(&xhci->lock);
 
@@ -1080,7 +1098,7 @@ int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
  set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
 
  spin_lock_irq(&xhci->lock);
- if (xhci->quirks & XHCI_RESET_ON_RESUME)
+ if ((xhci->quirks & XHCI_RESET_ON_RESUME) || xhci->broken_suspend)
  hibernated = true;
 
  if (!hibernated) {
diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
index 6230a578324c..5e56e8b9ed92 100644
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
@@ -1846,6 +1846,7 @@ struct xhci_hcd {
 #define XHCI_SUSPEND_DELAY BIT_ULL(30)
 #define XHCI_INTEL_USB_ROLE_SW BIT_ULL(31)
 #define XHCI_ZERO_64B_REGS BIT_ULL(32)
+#define XHCI_SNPS_BROKEN_SUSPEND    BIT_ULL(35)
 
  unsigned int num_active_eps;
  unsigned int limit_active_eps;
@@ -1875,6 +1876,8 @@ struct xhci_hcd {
  void *dbc;
  /* platform-specific data -- must come last */
  unsigned long priv[0] __aligned(sizeof(s64));
+ /* Broken Suspend flag for SNPS Suspend resume issue */
+ u8 broken_suspend;
 };
 
 /* Platform specific overrides to generic XHCI hc_driver ops */
--
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[OEM-B] [PATCH] xhci: workaround CSS timeout on AMD SNPS 3.0 xHC

Kai-Heng Feng
In reply to this post by Kai-Heng Feng
From: Sandeep Singh <[hidden email]>

BugLink: https://bugs.launchpad.net/bugs/1806838

Occasionally AMD SNPS 3.0 xHC does not respond to
CSS when set, also it does not flag anything on SRE and HCE
to point the internal xHC errors on USBSTS register. This stalls
the entire system wide suspend and there is no point in stalling
just because of xHC CSS is not responding.

To work around this problem, if the xHC does not flag
anything on SRE and HCE, we can skip the CSS
timeout and allow the system to continue the suspend. Once the
system resume happens we can internally reset the controller
using XHCI_RESET_ON_RESUME quirk

Signed-off-by: Shyam Sundar S K <[hidden email]>
Signed-off-by: Sandeep Singh <[hidden email]>
cc: Nehal Shah <[hidden email]>
Cc: <[hidden email]>
Tested-by: Kai-Heng Feng <[hidden email]>
Signed-off-by: Mathias Nyman <[hidden email]>
(backported from commit b5282b66f0dfe6e76644c5195ec6aa3de15fefa3 git://git.kernel.org/pub/scm/linux/kernel/git/mnyman/xhci.git for-usb-linus)
Signed-off-by: Kai-Heng Feng <[hidden email]>
---
 drivers/usb/host/xhci-pci.c |  4 ++++
 drivers/usb/host/xhci.c     | 26 ++++++++++++++++++++++----
 drivers/usb/host/xhci.h     |  3 +++
 3 files changed, 29 insertions(+), 4 deletions(-)

diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c
index ea19ff66430e..b7d9d3a2fbb3 100644
--- a/drivers/usb/host/xhci-pci.c
+++ b/drivers/usb/host/xhci-pci.c
@@ -139,6 +139,10 @@ static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
  pdev->device == 0x43bb))
  xhci->quirks |= XHCI_SUSPEND_DELAY;
 
+ if (pdev->vendor == PCI_VENDOR_ID_AMD &&
+    (pdev->device == 0x15e0 || pdev->device == 0x15e1))
+ xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND;
+
  if (pdev->vendor == PCI_VENDOR_ID_AMD)
  xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 
diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index 7479937f1471..92d006b10124 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -965,6 +965,7 @@ int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
  unsigned int delay = XHCI_MAX_HALT_USEC;
  struct usb_hcd *hcd = xhci_to_hcd(xhci);
  u32 command;
+ u32 res;
 
  if (!hcd->state)
  return 0;
@@ -1018,11 +1019,28 @@ int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
  command = readl(&xhci->op_regs->command);
  command |= CMD_CSS;
  writel(command, &xhci->op_regs->command);
+ xhci->broken_suspend = 0;
  if (xhci_handshake(&xhci->op_regs->status,
  STS_SAVE, 0, 10 * 1000)) {
- xhci_warn(xhci, "WARN: xHC save state timeout\n");
- spin_unlock_irq(&xhci->lock);
- return -ETIMEDOUT;
+ /*
+ * AMD SNPS xHC 3.0 occasionally does not clear the
+ * SSS bit of USBSTS and when driver tries to poll
+ * to see if the xHC clears BIT(8) which never happens
+ * and driver assumes that controller is not responding
+ * and times out. To workaround this, its good to check
+ * if SRE and HCE bits are not set (as per xhci
+ * Section 5.4.2) and bypass the timeout.
+ */
+ res = readl(&xhci->op_regs->status);
+ if ((xhci->quirks & XHCI_SNPS_BROKEN_SUSPEND) &&
+    (((res & STS_SRE) == 0) &&
+ ((res & STS_HCE) == 0))) {
+ xhci->broken_suspend = 1;
+ } else {
+ xhci_warn(xhci, "WARN: xHC save state timeout\n");
+ spin_unlock_irq(&xhci->lock);
+ return -ETIMEDOUT;
+ }
  }
  spin_unlock_irq(&xhci->lock);
 
@@ -1075,7 +1093,7 @@ int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
  set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
 
  spin_lock_irq(&xhci->lock);
- if (xhci->quirks & XHCI_RESET_ON_RESUME)
+ if ((xhci->quirks & XHCI_RESET_ON_RESUME) || xhci->broken_suspend)
  hibernated = true;
 
  if (!hibernated) {
diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
index deeac46221c6..9e08526aa671 100644
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
@@ -1844,6 +1844,7 @@ struct xhci_hcd {
 #define XHCI_INTEL_USB_ROLE_SW BIT_ULL(31)
 #define XHCI_ZERO_64B_REGS BIT_ULL(32)
 #define XHCI_DEFAULT_PM_RUNTIME_ALLOW BIT_ULL(33)
+#define XHCI_SNPS_BROKEN_SUSPEND    BIT_ULL(35)
 
  unsigned int num_active_eps;
  unsigned int limit_active_eps;
@@ -1873,6 +1874,8 @@ struct xhci_hcd {
  void *dbc;
  /* platform-specific data -- must come last */
  unsigned long priv[0] __aligned(sizeof(s64));
+ /* Broken Suspend flag for SNPS Suspend resume issue */
+ u8 broken_suspend;
 };
 
 /* Platform specific overrides to generic XHCI hc_driver ops */
--
2.17.1


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ACK / APPLIED[D]: [SRU] [B/C/D/Unstable/OEM-B] [PATCH 0/1] Workaround CSS timeout on AMD SNPS 3.0 xHC

Seth Forshee
In reply to this post by Kai-Heng Feng
On Wed, Dec 05, 2018 at 04:32:50PM +0800, Kai-Heng Feng wrote:

> BugLink: https://bugs.launchpad.net/bugs/1806838
>
> [Impact]
> Raven Ridge xHC may fail to suspend, causes the USB stops working, and
> blocks the system entering system-wide suspend.
>
> [Fix]
> It's a hardware/firmware bug, workarounded by bailing out suspend
> function if it ever fails, and reset the xHC in next resume function.
>
> [Test]
> After applying the patch, the USB works, and the system can enter S3
> consecutively.
>
> [Regression Potential]
> Minimal. This workaround only applies to AMD Raven Ridge xHC.

Cherry picks from upstream and maintainer tree, limited scope.

Acked-by: Seth Forshee <[hidden email]>

Applied to disco/master-next, thanks!

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ACK: [SRU] [B/C/D/Unstable/OEM-B] [PATCH 0/1] Workaround CSS timeout on AMD SNPS 3.0 xHC

Khaled Elmously
In reply to this post by Kai-Heng Feng
On 2018-12-05 16:32:50 , Kai-Heng Feng wrote:

> BugLink: https://bugs.launchpad.net/bugs/1806838
>
> [Impact]
> Raven Ridge xHC may fail to suspend, causes the USB stops working, and
> blocks the system entering system-wide suspend.
>
> [Fix]
> It's a hardware/firmware bug, workarounded by bailing out suspend
> function if it ever fails, and reset the xHC in next resume function.
>
> [Test]
> After applying the patch, the USB works, and the system can enter S3
> consecutively.
>
> [Regression Potential]
> Minimal. This workaround only applies to AMD Raven Ridge xHC.
>
> Sandeep Singh (1):
>   xhci: workaround CSS timeout on AMD SNPS 3.0 xHC
>
>  drivers/usb/host/xhci-pci.c |  4 ++++
>  drivers/usb/host/xhci.c     | 26 ++++++++++++++++++++++----
>  drivers/usb/host/xhci.h     |  3 +++
>  3 files changed, 29 insertions(+), 4 deletions(-)
>

Acked-by: Khalid Elmously <[hidden email]>
 

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[Acked] [SRU] [B/C/D/Unstable/OEM-B] [PATCH 0/1] Workaround CSS timeout on AMD SNPS 3.0 xHC

Andy Whitcroft-3
In reply to this post by Kai-Heng Feng
On Wed, Dec 05, 2018 at 04:32:50PM +0800, Kai-Heng Feng wrote:

> BugLink: https://bugs.launchpad.net/bugs/1806838
>
> [Impact]
> Raven Ridge xHC may fail to suspend, causes the USB stops working, and
> blocks the system entering system-wide suspend.
>
> [Fix]
> It's a hardware/firmware bug, workarounded by bailing out suspend
> function if it ever fails, and reset the xHC in next resume function.
>
> [Test]
> After applying the patch, the USB works, and the system can enter S3
> consecutively.
>
> [Regression Potential]
> Minimal. This workaround only applies to AMD Raven Ridge xHC.
>
> Sandeep Singh (1):
>   xhci: workaround CSS timeout on AMD SNPS 3.0 xHC
>
>  drivers/usb/host/xhci-pci.c |  4 ++++
>  drivers/usb/host/xhci.c     | 26 ++++++++++++++++++++++----
>  drivers/usb/host/xhci.h     |  3 +++
>  3 files changed, 29 insertions(+), 4 deletions(-)

Acked-by: Andy Whitcroft <[hidden email]>

-apw

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APPLIED[B/C]/cmnt: [SRU] [B/C/D/Unstable/OEM-B] [PATCH 0/1] Workaround CSS timeout on AMD SNPS 3.0 xHC

Kleber Souza
In reply to this post by Kai-Heng Feng
On 12/5/18 9:32 AM, Kai-Heng Feng wrote:

> BugLink: https://bugs.launchpad.net/bugs/1806838
>
> [Impact]
> Raven Ridge xHC may fail to suspend, causes the USB stops working, and
> blocks the system entering system-wide suspend.
>
> [Fix]
> It's a hardware/firmware bug, workarounded by bailing out suspend
> function if it ever fails, and reset the xHC in next resume function.
>
> [Test]
> After applying the patch, the USB works, and the system can enter S3
> consecutively.
>
> [Regression Potential]
> Minimal. This workaround only applies to AMD Raven Ridge xHC.
>
> Sandeep Singh (1):
>   xhci: workaround CSS timeout on AMD SNPS 3.0 xHC
>
>  drivers/usb/host/xhci-pci.c |  4 ++++
>  drivers/usb/host/xhci.c     | 26 ++++++++++++++++++++++----
>  drivers/usb/host/xhci.h     |  3 +++
>  3 files changed, 29 insertions(+), 4 deletions(-)
>
Applied the Bionic patches to bionic/master-next branch, and the Cosmic
one to cosmic/master-next-backlog branch (to be picked up for the next
cycle).


Thank you,

Kleber


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