[SRU][B/OEM-B][PATCH 0/3] screen displays abnormally on the lenovo M715 with the AMD GPU (Radeon Vega 8 Mobile, rev ca, 1002:15dd)

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[SRU][B/OEM-B][PATCH 0/3] screen displays abnormally on the lenovo M715 with the AMD GPU (Radeon Vega 8 Mobile, rev ca, 1002:15dd)

Hui Wang
BugLink: https://bugs.launchpad.net/bugs/1791569

These patches are in the 4.16-rcN already, no need to send them to cosmic.

[Impact]
On the machine of Lenovo M715, there is an AMD GPU (1022:15dd rev ca), when it
switchs to amdgpufb, the screen displays abnormally, we tested with a couple monitors,
all of them can reproduce this issue.

[Fix]
Backported 3 patches from mainline kernel, all of them focus on the change of
disable_vga(). After applying these 3 patches, the issue disappears.


[Test Case]
boot the system, run glxgears, everything works well

[Regression Potential]
Very low, these patches come from upstream, and I have tested them on at least 6 different
lenovo machines and those machines have different AMD GPUs on them, all of them worked
as well as before.



Bhawanpreet Lakha (1):
  drm/amd/display: Fix takover from VGA mode

Clark Zheng (1):
  drm/amd/display: Refine disable VGA

Eric Yang (1):
  drm/amd/display: early return if not in vga mode in disable_vga

 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h     | 17 ++++++++++++++-
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 24 ++++++++++++++++++++++
 2 files changed, 40 insertions(+), 1 deletion(-)

--
2.7.4


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[SRU][B/OEM-B][PATCH 1/3] drm/amd/display: Fix takover from VGA mode

Hui Wang
From: Bhawanpreet Lakha <[hidden email]>

BugLink: https://bugs.launchpad.net/bugs/1796786

HW Engineer's Notes:
 During switch from vga->extended, if we set the VGA_TEST_ENABLE and then
 hit the VGA_TEST_RENDER_START, then the DCHUBP timing gets updated correctly.
 Then vBIOS will have it poll for the VGA_TEST_RENDER_DONE and unset
 VGA_TEST_ENABLE, to leave it in the same state as before.

Signed-off-by: Bhawanpreet Lakha <[hidden email]>
Reviewed-by: Tony Cheng <[hidden email]>
Acked-by: Harry Wentland <[hidden email]>
Signed-off-by: Alex Deucher <[hidden email]>
(backported from commit bd9bc355be45dd2295ca746aa05b058be4cf94cc)
Signed-off-by: Hui Wang <[hidden email]>
---
 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h            | 11 +++++++++--
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 10 ++++++++++
 2 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index 5250615..1774ab1 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -240,6 +240,7 @@
  SR(D2VGA_CONTROL), \
  SR(D3VGA_CONTROL), \
  SR(D4VGA_CONTROL), \
+ SR(VGA_TEST_CONTROL), \
  SR(DC_IP_REQUEST_CNTL), \
  BL_REG_LIST()
 
@@ -342,6 +343,7 @@ struct dce_hwseq_registers {
  uint32_t D2VGA_CONTROL;
  uint32_t D3VGA_CONTROL;
  uint32_t D4VGA_CONTROL;
+ uint32_t VGA_TEST_CONTROL;
  /* MMHUB registers. read only. temporary hack */
  uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32;
  uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
@@ -501,7 +503,9 @@ struct dce_hwseq_registers {
  HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \
  HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
  HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
- HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
+ HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh), \
+ HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\
+ HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh)
 
 #define HWSEQ_REG_FIELD_LIST(type) \
  type DCFE_CLOCK_ENABLE; \
@@ -591,7 +595,10 @@ struct dce_hwseq_registers {
  type DOMAIN7_PGFSM_PWR_STATUS; \
  type DCFCLK_GATE_DIS; \
  type DCHUBBUB_GLOBAL_TIMER_REFDIV; \
- type DENTIST_DPPCLK_WDIVIDER;
+ type DENTIST_DPPCLK_WDIVIDER; \
+ type DENTIST_DISPCLK_WDIVIDER; \
+ type VGA_TEST_ENABLE; \
+ type VGA_TEST_RENDER_START;
 
 struct dce_hwseq_shift {
  HWSEQ_REG_FIELD_LIST(uint8_t)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 05dc01e..a930846 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -380,6 +380,16 @@ static void disable_vga(
  REG_WRITE(D2VGA_CONTROL, 0);
  REG_WRITE(D3VGA_CONTROL, 0);
  REG_WRITE(D4VGA_CONTROL, 0);
+
+ /* HW Engineer's Notes:
+ *  During switch from vga->extended, if we set the VGA_TEST_ENABLE and
+ *  then hit the VGA_TEST_RENDER_START, then the DCHUBP timing gets updated correctly.
+ *
+ *  Then vBIOS will have it poll for the VGA_TEST_RENDER_DONE and unset
+ *  VGA_TEST_ENABLE, to leave it in the same state as before.
+ */
+ REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_ENABLE, 1);
+ REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_RENDER_START, 1);
 }
 
 static void dpp_pg_control(
--
2.7.4


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[SRU][B/OEM-B][PATCH 2/3] drm/amd/display: early return if not in vga mode in disable_vga

Hui Wang
In reply to this post by Hui Wang
From: Eric Yang <[hidden email]>

BugLink: https://bugs.launchpad.net/bugs/1796786

The work around for hw bug causes S3 resume failure. Don't execute
disable vga logic if not in vga mode.

Signed-off-by: Eric Yang <[hidden email]>
Reviewed-by: Tony Cheng <[hidden email]>
Acked-by: Harry Wentland <[hidden email]>
Signed-off-by: Alex Deucher <[hidden email]>
(cherry picked from commit abca24007e0838ee8bfff37a188bf8df00703c52)
Signed-off-by: Hui Wang <[hidden email]>
---
 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h            | 10 ++++++----
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 10 +++++++---
 2 files changed, 13 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index 1774ab1..d5494f7 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -502,10 +502,11 @@ struct dce_hwseq_registers {
  HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \
  HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \
  HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
- HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
- HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh), \
+ HWS_SF(, D1VGA_CONTROL, D1VGA_MODE_ENABLE, mask_sh),\
  HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\
- HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh)
+ HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh),\
+ HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
+ HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
 
 #define HWSEQ_REG_FIELD_LIST(type) \
  type DCFE_CLOCK_ENABLE; \
@@ -598,7 +599,8 @@ struct dce_hwseq_registers {
  type DENTIST_DPPCLK_WDIVIDER; \
  type DENTIST_DISPCLK_WDIVIDER; \
  type VGA_TEST_ENABLE; \
- type VGA_TEST_RENDER_START;
+ type VGA_TEST_RENDER_START; \
+ type D1VGA_MODE_ENABLE;
 
 struct dce_hwseq_shift {
  HWSEQ_REG_FIELD_LIST(uint8_t)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index a930846..17ffaed 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -376,10 +376,14 @@ static void enable_power_gating_plane(
 static void disable_vga(
  struct dce_hwseq *hws)
 {
+ unsigned int in_vga_mode = 0;
+
+ REG_GET(D1VGA_CONTROL, D1VGA_MODE_ENABLE, &in_vga_mode);
+
+ if (in_vga_mode == 0)
+ return;
+
  REG_WRITE(D1VGA_CONTROL, 0);
- REG_WRITE(D2VGA_CONTROL, 0);
- REG_WRITE(D3VGA_CONTROL, 0);
- REG_WRITE(D4VGA_CONTROL, 0);
 
  /* HW Engineer's Notes:
  *  During switch from vga->extended, if we set the VGA_TEST_ENABLE and
--
2.7.4


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[SRU][B/OEM-B][PATCH 3/3] drm/amd/display: Refine disable VGA

Hui Wang
In reply to this post by Hui Wang
From: Clark Zheng <[hidden email]>

BugLink: https://bugs.launchpad.net/bugs/1796786

bad case won't follow normal sense, it will not enable vga1 as usual, but vga2,3,4 is on.

Signed-off-by: Clark Zheng <[hidden email]>
Reviewed-by: Tony Cheng <[hidden email]>
Acked-by: Alex Deucher <[hidden email]>
Signed-off-by: Alex Deucher <[hidden email]>
(cherry picked from commit 219be9dda6137bc9759c449bbff5d4394fe73382)
Signed-off-by: Hui Wang <[hidden email]>
---
 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h       |  8 +++++++-
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c    | 20 +++++++++++++++-----
 2 files changed, 22 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index d5494f7..a36b846 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -503,6 +503,9 @@ struct dce_hwseq_registers {
  HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \
  HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
  HWS_SF(, D1VGA_CONTROL, D1VGA_MODE_ENABLE, mask_sh),\
+ HWS_SF(, D2VGA_CONTROL, D2VGA_MODE_ENABLE, mask_sh),\
+ HWS_SF(, D3VGA_CONTROL, D3VGA_MODE_ENABLE, mask_sh),\
+ HWS_SF(, D4VGA_CONTROL, D4VGA_MODE_ENABLE, mask_sh),\
  HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\
  HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh),\
  HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
@@ -600,7 +603,10 @@ struct dce_hwseq_registers {
  type DENTIST_DISPCLK_WDIVIDER; \
  type VGA_TEST_ENABLE; \
  type VGA_TEST_RENDER_START; \
- type D1VGA_MODE_ENABLE;
+ type D1VGA_MODE_ENABLE; \
+ type D2VGA_MODE_ENABLE; \
+ type D3VGA_MODE_ENABLE; \
+ type D4VGA_MODE_ENABLE;
 
 struct dce_hwseq_shift {
  HWSEQ_REG_FIELD_LIST(uint8_t)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 17ffaed..cc44ce5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -376,14 +376,24 @@ static void enable_power_gating_plane(
 static void disable_vga(
  struct dce_hwseq *hws)
 {
- unsigned int in_vga_mode = 0;
-
- REG_GET(D1VGA_CONTROL, D1VGA_MODE_ENABLE, &in_vga_mode);
-
- if (in_vga_mode == 0)
+ unsigned int in_vga1_mode = 0;
+ unsigned int in_vga2_mode = 0;
+ unsigned int in_vga3_mode = 0;
+ unsigned int in_vga4_mode = 0;
+
+ REG_GET(D1VGA_CONTROL, D1VGA_MODE_ENABLE, &in_vga1_mode);
+ REG_GET(D2VGA_CONTROL, D2VGA_MODE_ENABLE, &in_vga2_mode);
+ REG_GET(D3VGA_CONTROL, D3VGA_MODE_ENABLE, &in_vga3_mode);
+ REG_GET(D4VGA_CONTROL, D4VGA_MODE_ENABLE, &in_vga4_mode);
+
+ if (in_vga1_mode == 0 && in_vga2_mode == 0 &&
+ in_vga3_mode == 0 && in_vga4_mode == 0)
  return;
 
  REG_WRITE(D1VGA_CONTROL, 0);
+ REG_WRITE(D2VGA_CONTROL, 0);
+ REG_WRITE(D3VGA_CONTROL, 0);
+ REG_WRITE(D4VGA_CONTROL, 0);
 
  /* HW Engineer's Notes:
  *  During switch from vga->extended, if we set the VGA_TEST_ENABLE and
--
2.7.4


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Re: [SRU][B/OEM-B][PATCH 0/3] screen displays abnormally on the lenovo M715 with the AMD GPU (Radeon Vega 8 Mobile, rev ca, 1002:15dd)

Hui Wang
In reply to this post by Hui Wang
On 2018年10月09日 12:54, Hui Wang wrote:
> BugLink: https://bugs.launchpad.net/bugs/1791569
Sorry it should be: BugLink: https://bugs.launchpad.net/bugs/1796786

Other parts are fine. please review them.

>
> These patches are in the 4.16-rcN already, no need to send them to cosmic.
>
> [Impact]
> On the machine of Lenovo M715, there is an AMD GPU (1022:15dd rev ca), when it
> switchs to amdgpufb, the screen displays abnormally, we tested with a couple monitors,
> all of them can reproduce this issue.
>
> [Fix]
> Backported 3 patches from mainline kernel, all of them focus on the change of
> disable_vga(). After applying these 3 patches, the issue disappears.
>
>
> [Test Case]
> boot the system, run glxgears, everything works well
>
> [Regression Potential]
> Very low, these patches come from upstream, and I have tested them on at least 6 different
> lenovo machines and those machines have different AMD GPUs on them, all of them worked
> as well as before.
>
>
>
> Bhawanpreet Lakha (1):
>    drm/amd/display: Fix takover from VGA mode
>
> Clark Zheng (1):
>    drm/amd/display: Refine disable VGA
>
> Eric Yang (1):
>    drm/amd/display: early return if not in vga mode in disable_vga
>
>   drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h     | 17 ++++++++++++++-
>   .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 24 ++++++++++++++++++++++
>   2 files changed, 40 insertions(+), 1 deletion(-)
>


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ACK/Cmnt: [SRU][B/OEM-B][PATCH 0/3] screen displays abnormally on the lenovo M715 with the AMD GPU (Radeon Vega 8 Mobile, rev ca, 1002:15dd)

Stefan Bader-2
In reply to this post by Hui Wang
On 09.10.2018 06:54, Hui Wang wrote:

> BugLink: https://bugs.launchpad.net/bugs/1791569
>
> These patches are in the 4.16-rcN already, no need to send them to cosmic.
>
> [Impact]
> On the machine of Lenovo M715, there is an AMD GPU (1022:15dd rev ca), when it
> switchs to amdgpufb, the screen displays abnormally, we tested with a couple monitors,
> all of them can reproduce this issue.
>
> [Fix]
> Backported 3 patches from mainline kernel, all of them focus on the change of
> disable_vga(). After applying these 3 patches, the issue disappears.
>
>
> [Test Case]
> boot the system, run glxgears, everything works well
>
> [Regression Potential]
> Very low, these patches come from upstream, and I have tested them on at least 6 different
> lenovo machines and those machines have different AMD GPUs on them, all of them worked
> as well as before.
>
>
>
> Bhawanpreet Lakha (1):
>   drm/amd/display: Fix takover from VGA mode
>
> Clark Zheng (1):
>   drm/amd/display: Refine disable VGA
>
> Eric Yang (1):
>   drm/amd/display: early return if not in vga mode in disable_vga
>
>  drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h     | 17 ++++++++++++++-
>  .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 24 ++++++++++++++++++++++
>  2 files changed, 40 insertions(+), 1 deletion(-)
>
The changes themselves are rather incomprehensible and thus not easy to look at.
However all for the same driver and some successful regression testing done. So
with the (->update buglink) buglink replaced by the one from this cover email:

Acked-by: Stefan Bader <[hidden email]>


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ACK: [SRU][B/OEM-B][PATCH 0/3] screen displays abnormally on the lenovo M715 with the AMD GPU (Radeon Vega 8 Mobile, rev ca, 1002:15dd)

Kleber Souza
In reply to this post by Hui Wang
On 10/09/18 06:54, Hui Wang wrote:

> BugLink: https://bugs.launchpad.net/bugs/1791569
>
> These patches are in the 4.16-rcN already, no need to send them to cosmic.
>
> [Impact]
> On the machine of Lenovo M715, there is an AMD GPU (1022:15dd rev ca), when it
> switchs to amdgpufb, the screen displays abnormally, we tested with a couple monitors,
> all of them can reproduce this issue.
>
> [Fix]
> Backported 3 patches from mainline kernel, all of them focus on the change of
> disable_vga(). After applying these 3 patches, the issue disappears.
>
>
> [Test Case]
> boot the system, run glxgears, everything works well
>
> [Regression Potential]
> Very low, these patches come from upstream, and I have tested them on at least 6 different
> lenovo machines and those machines have different AMD GPUs on them, all of them worked
> as well as before.
>
>
>
> Bhawanpreet Lakha (1):
>   drm/amd/display: Fix takover from VGA mode
>
> Clark Zheng (1):
>   drm/amd/display: Refine disable VGA
>
> Eric Yang (1):
>   drm/amd/display: early return if not in vga mode in disable_vga
>
>  drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h     | 17 ++++++++++++++-
>  .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 24 ++++++++++++++++++++++
>  2 files changed, 40 insertions(+), 1 deletion(-)
>

All changes upstream, don't seem too intrusive and well tested for
regressions. So:

Acked-by: Kleber Sacilotto de Souza <[hidden email]>

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