[SRU][Bionic][PATCH 0/5] TC filters are broken on Mellanox after upstream stable updates (LP: #1842502)

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[SRU][Bionic][PATCH 0/5] TC filters are broken on Mellanox after upstream stable updates (LP: #1842502)

Juerg Haefliger
[Impact]

Mellanox TC filters don't work for some key rules after the Bionic 4.15 stable patchset 2019-07-12 update (LP: #1836426). The offending commit is ("net/mlx5e: Set vlan masks for all offloaded TC rules").

This causes fatal network connectivity issues for projects that use the Mellanox ConnectX 5 NIC.

[Test Case]

TBD.

[Fix]

Backport the following upstream commit (which fixes the offending commit) and its prerequisites:
d3a80bb5a3ea ("net/mlx5e: Don't match on vlan non-existence if ethertype is wildcarded")

[Regression Potential]

Low. Changes are isolated and limited to the mlx5_core driver and all commits are in upstream stable v4.19.y.

[Original description]

The following upstream fix was missing from the latest upstream stable update (LP: # and LP1839376: #1839213):

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=d3a80bb5a3eac311ddf28387402593977574460d

Or Gerlitz (4):
  net/mlx5e: Properly order min inline mode setup while parsing TC
    matches
  net/mlx5e: Get the required HW match level while parsing TC flow
    matches
  net/mlx5e: Always use the match level enum when parsing TC rule match
  net/mlx5e: Don't match on vlan non-existence if ethertype is
    wildcarded

Saeed Mahameed (1):
  net/mlx5e: Remove redundant vport context vlan update

 .../net/ethernet/mellanox/mlx5/core/en_fs.c   |   1 -
 .../net/ethernet/mellanox/mlx5/core/en_tc.c   | 146 ++++++++++--------
 .../net/ethernet/mellanox/mlx5/core/eswitch.h |   7 +
 3 files changed, 92 insertions(+), 62 deletions(-)

--
2.20.1


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[SRU][Bionic][PATCH 1/5] net/mlx5e: Remove redundant vport context vlan update

Juerg Haefliger
From: Saeed Mahameed <[hidden email]>

BugLink: https://bugs.launchpad.net/bugs/1842502

In delete vlan flow an extra call to mlx5e_vport_context_update_vlans
was added by mistake, remove it.

Fixes: 86d722ad2c3b ("net/mlx5: Use flow steering infrastructure for mlx5_en")
Signed-off-by: Saeed Mahameed <[hidden email]>
Reviewed-by: Gal Pressman <[hidden email]>
(cherry picked from commit b8c931ba3c739b49bd536d35851712d838857757)
Signed-off-by: Juerg Haefliger <[hidden email]>
---
 drivers/net/ethernet/mellanox/mlx5/core/en_fs.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_fs.c b/drivers/net/ethernet/mellanox/mlx5/core/en_fs.c
index def513484845..c3585d1a2ccd 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en_fs.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_fs.c
@@ -277,7 +277,6 @@ static void mlx5e_del_vlan_rule(struct mlx5e_priv *priv,
  }
  break;
  case MLX5E_VLAN_RULE_TYPE_MATCH_CTAG_VID:
- mlx5e_vport_context_update_vlans(priv);
  if (priv->fs.vlan.active_cvlans_rule[vid]) {
  mlx5_del_flow_rules(priv->fs.vlan.active_cvlans_rule[vid]);
  priv->fs.vlan.active_cvlans_rule[vid] = NULL;
--
2.20.1


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[SRU][Bionic][PATCH 2/5] net/mlx5e: Properly order min inline mode setup while parsing TC matches

Juerg Haefliger
In reply to this post by Juerg Haefliger
From: Or Gerlitz <[hidden email]>

BugLink: https://bugs.launchpad.net/bugs/1842502

Set the initial value to none instead of L2, and set to L2
where the previous initial value was assumed. Make sure to
parse L2 matches before L3 matches and L3 before L4.

This is a pre-step to get the match level for more purposes
other than the validating the needed vs. actual inline level.

Signed-off-by: Or Gerlitz <[hidden email]>
Reviewed-by: Roi Dayan <[hidden email]>
Signed-off-by: Saeed Mahameed <[hidden email]>
(cherry picked from commit 547829004c98941f73d010c87c2111e29a6c03ae)
Signed-off-by: Juerg Haefliger <[hidden email]>
---
 .../net/ethernet/mellanox/mlx5/core/en_tc.c   | 129 +++++++++++-------
 1 file changed, 76 insertions(+), 53 deletions(-)

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c b/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
index 52e6e943e75a..9a869a008d47 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
@@ -730,7 +730,7 @@ static int __parse_cls_flower(struct mlx5e_priv *priv,
  u16 addr_type = 0;
  u8 ip_proto = 0;
 
- *min_inline = MLX5_INLINE_MODE_L2;
+ *min_inline = MLX5_INLINE_MODE_NONE;
 
  if (f->dissector->used_keys &
     ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) |
@@ -780,58 +780,6 @@ static int __parse_cls_flower(struct mlx5e_priv *priv,
  inner_headers);
  }
 
- if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_CONTROL)) {
- struct flow_dissector_key_control *key =
- skb_flow_dissector_target(f->dissector,
-  FLOW_DISSECTOR_KEY_CONTROL,
-  f->key);
-
- struct flow_dissector_key_control *mask =
- skb_flow_dissector_target(f->dissector,
-  FLOW_DISSECTOR_KEY_CONTROL,
-  f->mask);
- addr_type = key->addr_type;
-
- /* the HW doesn't support frag first/later */
- if (mask->flags & FLOW_DIS_FIRST_FRAG)
- return -EOPNOTSUPP;
-
- if (mask->flags & FLOW_DIS_IS_FRAGMENT) {
- MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
- MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
- key->flags & FLOW_DIS_IS_FRAGMENT);
-
- /* the HW doesn't need L3 inline to match on frag=no */
- if (key->flags & FLOW_DIS_IS_FRAGMENT)
- *min_inline = MLX5_INLINE_MODE_IP;
- }
- }
-
- if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_BASIC)) {
- struct flow_dissector_key_basic *key =
- skb_flow_dissector_target(f->dissector,
-  FLOW_DISSECTOR_KEY_BASIC,
-  f->key);
- struct flow_dissector_key_basic *mask =
- skb_flow_dissector_target(f->dissector,
-  FLOW_DISSECTOR_KEY_BASIC,
-  f->mask);
- ip_proto = key->ip_proto;
-
- MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
- ntohs(mask->n_proto));
- MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
- ntohs(key->n_proto));
-
- MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
- mask->ip_proto);
- MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
- key->ip_proto);
-
- if (mask->ip_proto)
- *min_inline = MLX5_INLINE_MODE_IP;
- }
-
  if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
  struct flow_dissector_key_eth_addrs *key =
  skb_flow_dissector_target(f->dissector,
@@ -855,6 +803,9 @@ static int __parse_cls_flower(struct mlx5e_priv *priv,
  ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
      smac_47_16),
  key->src);
+
+ if (!is_zero_ether_addr(mask->src) || !is_zero_ether_addr(mask->dst))
+ *min_inline = MLX5_INLINE_MODE_L2;
  }
 
  if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_VLAN)) {
@@ -875,12 +826,82 @@ static int __parse_cls_flower(struct mlx5e_priv *priv,
 
  MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio, mask->vlan_priority);
  MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, key->vlan_priority);
+
+ *min_inline = MLX5_INLINE_MODE_L2;
  }
  } else {
  MLX5_SET(fte_match_set_lyr_2_4, headers_c, svlan_tag, 1);
  MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
  }
 
+ if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_BASIC)) {
+ struct flow_dissector_key_basic *key =
+ skb_flow_dissector_target(f->dissector,
+  FLOW_DISSECTOR_KEY_BASIC,
+  f->key);
+ struct flow_dissector_key_basic *mask =
+ skb_flow_dissector_target(f->dissector,
+  FLOW_DISSECTOR_KEY_BASIC,
+  f->mask);
+ MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
+ ntohs(mask->n_proto));
+ MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
+ ntohs(key->n_proto));
+
+ if (mask->n_proto)
+ *min_inline = MLX5_INLINE_MODE_L2;
+ }
+
+ if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_CONTROL)) {
+ struct flow_dissector_key_control *key =
+ skb_flow_dissector_target(f->dissector,
+  FLOW_DISSECTOR_KEY_CONTROL,
+  f->key);
+
+ struct flow_dissector_key_control *mask =
+ skb_flow_dissector_target(f->dissector,
+  FLOW_DISSECTOR_KEY_CONTROL,
+  f->mask);
+ addr_type = key->addr_type;
+
+ /* the HW doesn't support frag first/later */
+ if (mask->flags & FLOW_DIS_FIRST_FRAG)
+ return -EOPNOTSUPP;
+
+ if (mask->flags & FLOW_DIS_IS_FRAGMENT) {
+ MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
+ MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
+ key->flags & FLOW_DIS_IS_FRAGMENT);
+
+ /* the HW doesn't need L3 inline to match on frag=no */
+ if (!(key->flags & FLOW_DIS_IS_FRAGMENT))
+ *min_inline = MLX5_INLINE_MODE_L2;
+ /* ***  L2 attributes parsing up to here *** */
+ else
+ *min_inline = MLX5_INLINE_MODE_IP;
+ }
+ }
+
+ if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_BASIC)) {
+ struct flow_dissector_key_basic *key =
+ skb_flow_dissector_target(f->dissector,
+  FLOW_DISSECTOR_KEY_BASIC,
+  f->key);
+ struct flow_dissector_key_basic *mask =
+ skb_flow_dissector_target(f->dissector,
+  FLOW_DISSECTOR_KEY_BASIC,
+  f->mask);
+ ip_proto = key->ip_proto;
+
+ MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
+ mask->ip_proto);
+ MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
+ key->ip_proto);
+
+ if (mask->ip_proto)
+ *min_inline = MLX5_INLINE_MODE_IP;
+ }
+
  if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
  struct flow_dissector_key_ipv4_addrs *key =
  skb_flow_dissector_target(f->dissector,
@@ -965,6 +986,8 @@ static int __parse_cls_flower(struct mlx5e_priv *priv,
  *min_inline = MLX5_INLINE_MODE_IP;
  }
 
+ /* ***  L3 attributes parsing up to here *** */
+
  if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_PORTS)) {
  struct flow_dissector_key_ports *key =
  skb_flow_dissector_target(f->dissector,
--
2.20.1


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[SRU][Bionic][PATCH 3/5] net/mlx5e: Get the required HW match level while parsing TC flow matches

Juerg Haefliger
In reply to this post by Juerg Haefliger
From: Or Gerlitz <[hidden email]>

BugLink: https://bugs.launchpad.net/bugs/1842502

Introduce levels of matching on headers of offloaded flows
(none, L2, L3, L4) that follow the inline mode levels.

This is pre-step for us to offload flows without any
matches on headers.

Signed-off-by: Or Gerlitz <[hidden email]>
Reviewed-by: Roi Dayan <[hidden email]>
Signed-off-by: Saeed Mahameed <[hidden email]>
(backported from commit d708f902989b844907c5f7720abe67812a256c33)
[juergh: Adjusted context.]
Signed-off-by: Juerg Haefliger <[hidden email]>
---
 .../net/ethernet/mellanox/mlx5/core/en_tc.c   | 34 +++++++++----------
 .../net/ethernet/mellanox/mlx5/core/eswitch.h |  7 ++++
 2 files changed, 24 insertions(+), 17 deletions(-)

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c b/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
index 9a869a008d47..66210595fb58 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
@@ -721,7 +721,7 @@ static int parse_tunnel_attr(struct mlx5e_priv *priv,
 static int __parse_cls_flower(struct mlx5e_priv *priv,
       struct mlx5_flow_spec *spec,
       struct tc_cls_flower_offload *f,
-      u8 *min_inline)
+      u8 *match_level)
 {
  void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
        outer_headers);
@@ -730,7 +730,7 @@ static int __parse_cls_flower(struct mlx5e_priv *priv,
  u16 addr_type = 0;
  u8 ip_proto = 0;
 
- *min_inline = MLX5_INLINE_MODE_NONE;
+ *match_level = MLX5_MATCH_NONE;
 
  if (f->dissector->used_keys &
     ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) |
@@ -805,7 +805,7 @@ static int __parse_cls_flower(struct mlx5e_priv *priv,
  key->src);
 
  if (!is_zero_ether_addr(mask->src) || !is_zero_ether_addr(mask->dst))
- *min_inline = MLX5_INLINE_MODE_L2;
+ *match_level = MLX5_MATCH_L2;
  }
 
  if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_VLAN)) {
@@ -827,7 +827,7 @@ static int __parse_cls_flower(struct mlx5e_priv *priv,
  MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio, mask->vlan_priority);
  MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, key->vlan_priority);
 
- *min_inline = MLX5_INLINE_MODE_L2;
+ *match_level = MLX5_MATCH_L2;
  }
  } else {
  MLX5_SET(fte_match_set_lyr_2_4, headers_c, svlan_tag, 1);
@@ -849,7 +849,7 @@ static int __parse_cls_flower(struct mlx5e_priv *priv,
  ntohs(key->n_proto));
 
  if (mask->n_proto)
- *min_inline = MLX5_INLINE_MODE_L2;
+ *match_level = MLX5_MATCH_L2;
  }
 
  if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_CONTROL)) {
@@ -875,10 +875,10 @@ static int __parse_cls_flower(struct mlx5e_priv *priv,
 
  /* the HW doesn't need L3 inline to match on frag=no */
  if (!(key->flags & FLOW_DIS_IS_FRAGMENT))
- *min_inline = MLX5_INLINE_MODE_L2;
+ *match_level = MLX5_INLINE_MODE_L2;
  /* ***  L2 attributes parsing up to here *** */
  else
- *min_inline = MLX5_INLINE_MODE_IP;
+ *match_level = MLX5_INLINE_MODE_IP;
  }
  }
 
@@ -899,7 +899,7 @@ static int __parse_cls_flower(struct mlx5e_priv *priv,
  key->ip_proto);
 
  if (mask->ip_proto)
- *min_inline = MLX5_INLINE_MODE_IP;
+ *match_level = MLX5_MATCH_L3;
  }
 
  if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
@@ -926,7 +926,7 @@ static int __parse_cls_flower(struct mlx5e_priv *priv,
        &key->dst, sizeof(key->dst));
 
  if (mask->src || mask->dst)
- *min_inline = MLX5_INLINE_MODE_IP;
+ *match_level = MLX5_MATCH_L3;
  }
 
  if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
@@ -955,7 +955,7 @@ static int __parse_cls_flower(struct mlx5e_priv *priv,
 
  if (ipv6_addr_type(&mask->src) != IPV6_ADDR_ANY ||
     ipv6_addr_type(&mask->dst) != IPV6_ADDR_ANY)
- *min_inline = MLX5_INLINE_MODE_IP;
+ *match_level = MLX5_MATCH_L3;
  }
 
  if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_IP)) {
@@ -983,7 +983,7 @@ static int __parse_cls_flower(struct mlx5e_priv *priv,
  return -EOPNOTSUPP;
 
  if (mask->tos || mask->ttl)
- *min_inline = MLX5_INLINE_MODE_IP;
+ *match_level = MLX5_MATCH_L3;
  }
 
  /* ***  L3 attributes parsing up to here *** */
@@ -1028,7 +1028,7 @@ static int __parse_cls_flower(struct mlx5e_priv *priv,
  }
 
  if (mask->src || mask->dst)
- *min_inline = MLX5_INLINE_MODE_TCP_UDP;
+ *match_level = MLX5_MATCH_L4;
  }
 
  if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_TCP)) {
@@ -1047,7 +1047,7 @@ static int __parse_cls_flower(struct mlx5e_priv *priv,
  ntohs(key->flags));
 
  if (mask->flags)
- *min_inline = MLX5_INLINE_MODE_TCP_UDP;
+ *match_level = MLX5_MATCH_L4;
  }
 
  return 0;
@@ -1062,19 +1062,19 @@ static int parse_cls_flower(struct mlx5e_priv *priv,
  struct mlx5_eswitch *esw = dev->priv.eswitch;
  struct mlx5e_rep_priv *rpriv = priv->ppriv;
  struct mlx5_eswitch_rep *rep;
- u8 min_inline;
+ u8 match_level;
  int err;
 
- err = __parse_cls_flower(priv, spec, f, &min_inline);
+ err = __parse_cls_flower(priv, spec, f, &match_level);
 
  if (!err && (flow->flags & MLX5E_TC_FLOW_ESWITCH)) {
  rep = rpriv->rep;
  if (rep->vport != FDB_UPLINK_VPORT &&
     (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
-    esw->offloads.inline_mode < min_inline)) {
+    esw->offloads.inline_mode < match_level)) {
  netdev_warn(priv->netdev,
     "Flow is not offloaded due to min inline setting, required %d actual %d\n",
-    min_inline, esw->offloads.inline_mode);
+    match_level, esw->offloads.inline_mode);
  return -EOPNOTSUPP;
  }
  }
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h
index 10bf770675f3..bd9309b3da6f 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h
+++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h
@@ -247,6 +247,13 @@ enum {
 #define MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  0x4000
 #define MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH 0x8000
 
+enum mlx5_flow_match_level {
+ MLX5_MATCH_NONE = MLX5_INLINE_MODE_NONE,
+ MLX5_MATCH_L2 = MLX5_INLINE_MODE_L2,
+ MLX5_MATCH_L3 = MLX5_INLINE_MODE_IP,
+ MLX5_MATCH_L4 = MLX5_INLINE_MODE_TCP_UDP,
+};
+
 struct mlx5_esw_flow_attr {
  struct mlx5_eswitch_rep *in_rep;
  struct mlx5_eswitch_rep *out_rep;
--
2.20.1


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[SRU][Bionic][PATCH 4/5] net/mlx5e: Always use the match level enum when parsing TC rule match

Juerg Haefliger
In reply to this post by Juerg Haefliger
From: Or Gerlitz <[hidden email]>

BugLink: https://bugs.launchpad.net/bugs/1842502

We get the match level (none, l2, l3, l4) while going over the match
dissectors of an offloaded tc rule. When doing this, the match level
enum and the not min inline enum values should be used, fix that.

This worked accidentally b/c both enums have the same numerical values.

Fixes: d708f902989b ('net/mlx5e: Get the required HW match level while parsing TC flow matches')
Signed-off-by: Or Gerlitz <[hidden email]>
Reviewed-by: Roi Dayan <[hidden email]>
Signed-off-by: Saeed Mahameed <[hidden email]>
(cherry picked from commit 83621b7df6a646e550fd3d36db2e301cf9a5096b)
Signed-off-by: Juerg Haefliger <[hidden email]>
---
 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c b/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
index 66210595fb58..cb17eb25f696 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
@@ -875,10 +875,10 @@ static int __parse_cls_flower(struct mlx5e_priv *priv,
 
  /* the HW doesn't need L3 inline to match on frag=no */
  if (!(key->flags & FLOW_DIS_IS_FRAGMENT))
- *match_level = MLX5_INLINE_MODE_L2;
+ *match_level = MLX5_MATCH_L2;
  /* ***  L2 attributes parsing up to here *** */
  else
- *match_level = MLX5_INLINE_MODE_IP;
+ *match_level = MLX5_MATCH_L3;
  }
  }
 
--
2.20.1


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[SRU][Bionic][PATCH 5/5] net/mlx5e: Don't match on vlan non-existence if ethertype is wildcarded

Juerg Haefliger
In reply to this post by Juerg Haefliger
From: Or Gerlitz <[hidden email]>

BugLink: https://bugs.launchpad.net/bugs/1842502

For the "all" ethertype we should not care whether the packet has
vlans. Besides being wrong, the way we did it caused FW error
for rules such as:

tc filter add dev eth0 protocol all parent ffff: \
        prio 1 flower skip_sw action drop

b/c the matching meta-data (outer headers bit in struct mlx5_flow_spec)
wasn't set. Fix that by matching on vlan non-existence only if we were
also told to match on the ethertype.

Fixes: cee26487620b ('net/mlx5e: Set vlan masks for all offloaded TC rules')
Signed-off-by: Or Gerlitz <[hidden email]>
Reported-by: Slava Ovsiienko <[hidden email]>
Reviewed-by: Jianbo Liu <[hidden email]>
Reviewed-by: Roi Dayan <[hidden email]>
Signed-off-by: Saeed Mahameed <[hidden email]>
(backported from commit d3a80bb5a3eac311ddf28387402593977574460d)
[juergh: Adjusted for missing commit 699e96ddf47f ("net/mlx5e: Support
 offloading tc double vlan headers match").]
Signed-off-by: Juerg Haefliger <[hidden email]>
---
 .../net/ethernet/mellanox/mlx5/core/en_tc.c   | 63 ++++++++++---------
 1 file changed, 32 insertions(+), 31 deletions(-)

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c b/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
index cb17eb25f696..3c21b347895f 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
@@ -780,31 +780,21 @@ static int __parse_cls_flower(struct mlx5e_priv *priv,
  inner_headers);
  }
 
- if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
- struct flow_dissector_key_eth_addrs *key =
+ if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_BASIC)) {
+ struct flow_dissector_key_basic *key =
  skb_flow_dissector_target(f->dissector,
-  FLOW_DISSECTOR_KEY_ETH_ADDRS,
+  FLOW_DISSECTOR_KEY_BASIC,
   f->key);
- struct flow_dissector_key_eth_addrs *mask =
+ struct flow_dissector_key_basic *mask =
  skb_flow_dissector_target(f->dissector,
-  FLOW_DISSECTOR_KEY_ETH_ADDRS,
+  FLOW_DISSECTOR_KEY_BASIC,
   f->mask);
+ MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
+ ntohs(mask->n_proto));
+ MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
+ ntohs(key->n_proto));
 
- ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
-     dmac_47_16),
- mask->dst);
- ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
-     dmac_47_16),
- key->dst);
-
- ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
-     smac_47_16),
- mask->src);
- ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
-     smac_47_16),
- key->src);
-
- if (!is_zero_ether_addr(mask->src) || !is_zero_ether_addr(mask->dst))
+ if (mask->n_proto)
  *match_level = MLX5_MATCH_L2;
  }
 
@@ -829,26 +819,37 @@ static int __parse_cls_flower(struct mlx5e_priv *priv,
 
  *match_level = MLX5_MATCH_L2;
  }
- } else {
+ } else if (*match_level != MLX5_MATCH_NONE) {
  MLX5_SET(fte_match_set_lyr_2_4, headers_c, svlan_tag, 1);
  MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
+ *match_level = MLX5_MATCH_L2;
  }
 
- if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_BASIC)) {
- struct flow_dissector_key_basic *key =
+ if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
+ struct flow_dissector_key_eth_addrs *key =
  skb_flow_dissector_target(f->dissector,
-  FLOW_DISSECTOR_KEY_BASIC,
+  FLOW_DISSECTOR_KEY_ETH_ADDRS,
   f->key);
- struct flow_dissector_key_basic *mask =
+ struct flow_dissector_key_eth_addrs *mask =
  skb_flow_dissector_target(f->dissector,
-  FLOW_DISSECTOR_KEY_BASIC,
+  FLOW_DISSECTOR_KEY_ETH_ADDRS,
   f->mask);
- MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
- ntohs(mask->n_proto));
- MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
- ntohs(key->n_proto));
 
- if (mask->n_proto)
+ ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
+     dmac_47_16),
+ mask->dst);
+ ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
+     dmac_47_16),
+ key->dst);
+
+ ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
+     smac_47_16),
+ mask->src);
+ ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
+     smac_47_16),
+ key->src);
+
+ if (!is_zero_ether_addr(mask->src) || !is_zero_ether_addr(mask->dst))
  *match_level = MLX5_MATCH_L2;
  }
 
--
2.20.1


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ACK: [SRU][Bionic][PATCH 0/5] TC filters are broken on Mellanox after upstream stable updates (LP: #1842502)

Sultan Alsawaf
In reply to this post by Juerg Haefliger
On Wed, Sep 25, 2019 at 10:07:47AM +0200, Juerg Haefliger wrote:

> [Impact]
>
> Mellanox TC filters don't work for some key rules after the Bionic 4.15 stable patchset 2019-07-12 update (LP: #1836426). The offending commit is ("net/mlx5e: Set vlan masks for all offloaded TC rules").
>
> This causes fatal network connectivity issues for projects that use the Mellanox ConnectX 5 NIC.
>
> [Test Case]
>
> TBD.
>
> [Fix]
>
> Backport the following upstream commit (which fixes the offending commit) and its prerequisites:
> d3a80bb5a3ea ("net/mlx5e: Don't match on vlan non-existence if ethertype is wildcarded")
>
> [Regression Potential]
>
> Low. Changes are isolated and limited to the mlx5_core driver and all commits are in upstream stable v4.19.y.
>
> [Original description]
>
> The following upstream fix was missing from the latest upstream stable update (LP: # and LP1839376: #1839213):
>
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=d3a80bb5a3eac311ddf28387402593977574460d
>
> Or Gerlitz (4):
>   net/mlx5e: Properly order min inline mode setup while parsing TC
>     matches
>   net/mlx5e: Get the required HW match level while parsing TC flow
>     matches
>   net/mlx5e: Always use the match level enum when parsing TC rule match
>   net/mlx5e: Don't match on vlan non-existence if ethertype is
>     wildcarded
>
> Saeed Mahameed (1):
>   net/mlx5e: Remove redundant vport context vlan update
>
>  .../net/ethernet/mellanox/mlx5/core/en_fs.c   |   1 -
>  .../net/ethernet/mellanox/mlx5/core/en_tc.c   | 146 ++++++++++--------
>  .../net/ethernet/mellanox/mlx5/core/eswitch.h |   7 +
>  3 files changed, 92 insertions(+), 62 deletions(-)
>
> --
> 2.20.1
>
>
> --
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> [hidden email]
> https://lists.ubuntu.com/mailman/listinfo/kernel-team

Acked-by: Sultan Alsawaf <[hidden email]>

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ACK: [SRU][Bionic][PATCH 0/5] TC filters are broken on Mellanox after upstream stable updates (LP: #1842502)

Connor Kuehl
In reply to this post by Juerg Haefliger
On 9/25/19 1:07 AM, Juerg Haefliger wrote:

> [Impact]
>
> Mellanox TC filters don't work for some key rules after the Bionic 4.15 stable patchset 2019-07-12 update (LP: #1836426). The offending commit is ("net/mlx5e: Set vlan masks for all offloaded TC rules").
>
> This causes fatal network connectivity issues for projects that use the Mellanox ConnectX 5 NIC.
>
> [Test Case]
>
> TBD.
>
> [Fix]
>
> Backport the following upstream commit (which fixes the offending commit) and its prerequisites:
> d3a80bb5a3ea ("net/mlx5e: Don't match on vlan non-existence if ethertype is wildcarded")
>
> [Regression Potential]
>
> Low. Changes are isolated and limited to the mlx5_core driver and all commits are in upstream stable v4.19.y.
>
> [Original description]
>
> The following upstream fix was missing from the latest upstream stable update (LP: # and LP1839376: #1839213):
>
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=d3a80bb5a3eac311ddf28387402593977574460d
>
> Or Gerlitz (4):
>    net/mlx5e: Properly order min inline mode setup while parsing TC
>      matches
>    net/mlx5e: Get the required HW match level while parsing TC flow
>      matches
>    net/mlx5e: Always use the match level enum when parsing TC rule match
>    net/mlx5e: Don't match on vlan non-existence if ethertype is
>      wildcarded
>
> Saeed Mahameed (1):
>    net/mlx5e: Remove redundant vport context vlan update
>
>   .../net/ethernet/mellanox/mlx5/core/en_fs.c   |   1 -
>   .../net/ethernet/mellanox/mlx5/core/en_tc.c   | 146 ++++++++++--------
>   .../net/ethernet/mellanox/mlx5/core/eswitch.h |   7 +
>   3 files changed, 92 insertions(+), 62 deletions(-)
>

Acked-by: Connor Kuehl <[hidden email]>

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APPLIED: [SRU][Bionic][PATCH 0/5] TC filters are broken on Mellanox after upstream stable updates (LP: #1842502)

Khaled Elmously
In reply to this post by Juerg Haefliger
On 2019-09-25 10:07:47 , Juerg Haefliger wrote:

> [Impact]
>
> Mellanox TC filters don't work for some key rules after the Bionic 4.15 stable patchset 2019-07-12 update (LP: #1836426). The offending commit is ("net/mlx5e: Set vlan masks for all offloaded TC rules").
>
> This causes fatal network connectivity issues for projects that use the Mellanox ConnectX 5 NIC.
>
> [Test Case]
>
> TBD.
>
> [Fix]
>
> Backport the following upstream commit (which fixes the offending commit) and its prerequisites:
> d3a80bb5a3ea ("net/mlx5e: Don't match on vlan non-existence if ethertype is wildcarded")
>
> [Regression Potential]
>
> Low. Changes are isolated and limited to the mlx5_core driver and all commits are in upstream stable v4.19.y.
>
> [Original description]
>
> The following upstream fix was missing from the latest upstream stable update (LP: # and LP1839376: #1839213):
>
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=d3a80bb5a3eac311ddf28387402593977574460d
>
> Or Gerlitz (4):
>   net/mlx5e: Properly order min inline mode setup while parsing TC
>     matches
>   net/mlx5e: Get the required HW match level while parsing TC flow
>     matches
>   net/mlx5e: Always use the match level enum when parsing TC rule match
>   net/mlx5e: Don't match on vlan non-existence if ethertype is
>     wildcarded
>
> Saeed Mahameed (1):
>   net/mlx5e: Remove redundant vport context vlan update
>
>  .../net/ethernet/mellanox/mlx5/core/en_fs.c   |   1 -
>  .../net/ethernet/mellanox/mlx5/core/en_tc.c   | 146 ++++++++++--------
>  .../net/ethernet/mellanox/mlx5/core/eswitch.h |   7 +
>  3 files changed, 92 insertions(+), 62 deletions(-)
>
> --
> 2.20.1
>
>
> --
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> https://lists.ubuntu.com/mailman/listinfo/kernel-team

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