[SRU][Bionic] Update ThunderX2 implementation defined pmu core events

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[SRU][Bionic] Update ThunderX2 implementation defined pmu core events

Manoj Iyer
Please consider the following patch to ARM64 ThunderX2 PMU core events. The ARM architecture defines several events as part of the Performance Monitor Unit (PMU) Extension. In addition, Cavium has added "implementation defined" pmu core events, which Cavium deems most useful for analyzing performance. Currently perf does not list these "implementation defined" events.

The patch was tested by me on a Cavium ThunderX2 system and no
regressions were found.



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[PATCH] perf vendor events arm64: Update ThunderX2 implementation defined pmu core events

Manoj Iyer
From: Ganapatrao Kulkarni <[hidden email]>

BugLink: http://launchpad.net/bugs/1796904

Signed-off-by: Ganapatrao Kulkarni <[hidden email]>
Cc: Alexander Shishkin <[hidden email]>
Cc: Ganapatrao Kulkarni <[hidden email]>
Cc: Jan Glauber <[hidden email]>
Cc: Jayachandran C <[hidden email]>
Cc: Jiri Olsa <[hidden email]>
Cc: [hidden email]
Cc: Mark Rutland <[hidden email]>
Cc: Namhyung Kim <[hidden email]>
Cc: Peter Zijlstra <[hidden email]>
Cc: Robert Richter <[hidden email]>
Cc: Vadim Lomovtsev <[hidden email]>
Cc: Will Deacon <[hidden email]>
Link: http://lkml.kernel.org/r/20180731100251.23575-1-ganapatrao.kulkarni@...
Signed-off-by: Arnaldo Carvalho de Melo <[hidden email]>
(cherry picked from commit b9b77222d4ff6b5bb8f5d87fca20de0910618bb9)
Signed-off-by: Manoj Iyer <[hidden email]>
---
 .../arm64/cavium/thunderx2/core-imp-def.json  | 87 ++++++++++++++++++-
 1 file changed, 84 insertions(+), 3 deletions(-)

diff --git a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
index bc03c06c3918..752e47eb6977 100644
--- a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
+++ b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
@@ -11,6 +11,21 @@
     {
         "ArchStdEvent": "L1D_CACHE_REFILL_WR",
     },
+    {
+        "ArchStdEvent": "L1D_CACHE_REFILL_INNER",
+    },
+    {
+        "ArchStdEvent": "L1D_CACHE_REFILL_OUTER",
+    },
+    {
+        "ArchStdEvent": "L1D_CACHE_WB_VICTIM",
+    },
+    {
+        "ArchStdEvent": "L1D_CACHE_WB_CLEAN",
+    },
+    {
+        "ArchStdEvent": "L1D_CACHE_INVAL",
+    },
     {
         "ArchStdEvent": "L1D_TLB_REFILL_RD",
     },
@@ -23,10 +38,76 @@
     {
         "ArchStdEvent": "L1D_TLB_WR",
     },
+    {
+        "ArchStdEvent": "L2D_TLB_REFILL_RD",
+    },
+    {
+        "ArchStdEvent": "L2D_TLB_REFILL_WR",
+    },
+    {
+        "ArchStdEvent": "L2D_TLB_RD",
+    },
+    {
+        "ArchStdEvent": "L2D_TLB_WR",
+    },
     {
         "ArchStdEvent": "BUS_ACCESS_RD",
-   },
-   {
+    },
+    {
         "ArchStdEvent": "BUS_ACCESS_WR",
-   }
+    },
+    {
+        "ArchStdEvent": "MEM_ACCESS_RD",
+    },
+    {
+        "ArchStdEvent": "MEM_ACCESS_WR",
+    },
+    {
+        "ArchStdEvent": "UNALIGNED_LD_SPEC",
+    },
+    {
+        "ArchStdEvent": "UNALIGNED_ST_SPEC",
+    },
+    {
+        "ArchStdEvent": "UNALIGNED_LDST_SPEC",
+    },
+    {
+        "ArchStdEvent": "EXC_UNDEF",
+    },
+    {
+        "ArchStdEvent": "EXC_SVC",
+    },
+    {
+        "ArchStdEvent": "EXC_PABORT",
+    },
+    {
+        "ArchStdEvent": "EXC_DABORT",
+    },
+    {
+        "ArchStdEvent": "EXC_IRQ",
+    },
+    {
+        "ArchStdEvent": "EXC_FIQ",
+    },
+    {
+        "ArchStdEvent": "EXC_SMC",
+    },
+    {
+        "ArchStdEvent": "EXC_HVC",
+    },
+    {
+        "ArchStdEvent": "EXC_TRAP_PABORT",
+    },
+    {
+        "ArchStdEvent": "EXC_TRAP_DABORT",
+    },
+    {
+        "ArchStdEvent": "EXC_TRAP_OTHER",
+    },
+    {
+        "ArchStdEvent": "EXC_TRAP_IRQ",
+    },
+    {
+        "ArchStdEvent": "EXC_TRAP_FIQ",
+    }
 ]
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2.17.1


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Re: [SRU][Bionic] Update ThunderX2 implementation defined pmu core events

Seth Forshee
In reply to this post by Manoj Iyer
On Tue, Oct 09, 2018 at 09:52:44AM -0500, Manoj Iyer wrote:
> Please consider the following patch to ARM64 ThunderX2 PMU core events. The ARM architecture defines several events as part of the Performance Monitor Unit (PMU) Extension. In addition, Cavium has added "implementation defined" pmu core events, which Cavium deems most useful for analyzing performance. Currently perf does not list these "implementation defined" events.
>
> The patch was tested by me on a Cavium ThunderX2 system and no
> regressions were found.

I don't see this patch in cosmic, is it needed there too?

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Re: [SRU][Bionic] Update ThunderX2 implementation defined pmu core events

Manoj Iyer
On Wed, 10 Oct 2018, Seth Forshee wrote:

> On Tue, Oct 09, 2018 at 09:52:44AM -0500, Manoj Iyer wrote:
>> Please consider the following patch to ARM64 ThunderX2 PMU core events. The ARM architecture defines several events as part of the Performance Monitor Unit (PMU) Extension. In addition, Cavium has added "implementation defined" pmu core events, which Cavium deems most useful for analyzing performance. Currently perf does not list these "implementation defined" events.
>>
>> The patch was tested by me on a Cavium ThunderX2 system and no
>> regressions were found.
>
> I don't see this patch in cosmic, is it needed there too?

oops.. I did not catch that. Yes, please apply to Cosmic as well.

>
>

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============================

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ACK: [PATCH] perf vendor events arm64: Update ThunderX2 implementation defined pmu core events

Stefan Bader-2
In reply to this post by Manoj Iyer
On 09.10.2018 16:52, Manoj Iyer wrote:

> From: Ganapatrao Kulkarni <[hidden email]>
>
> BugLink: http://launchpad.net/bugs/1796904
>
> Signed-off-by: Ganapatrao Kulkarni <[hidden email]>
> Cc: Alexander Shishkin <[hidden email]>
> Cc: Ganapatrao Kulkarni <[hidden email]>
> Cc: Jan Glauber <[hidden email]>
> Cc: Jayachandran C <[hidden email]>
> Cc: Jiri Olsa <[hidden email]>
> Cc: [hidden email]
> Cc: Mark Rutland <[hidden email]>
> Cc: Namhyung Kim <[hidden email]>
> Cc: Peter Zijlstra <[hidden email]>
> Cc: Robert Richter <[hidden email]>
> Cc: Vadim Lomovtsev <[hidden email]>
> Cc: Will Deacon <[hidden email]>
> Link: http://lkml.kernel.org/r/20180731100251.23575-1-ganapatrao.kulkarni@...
> Signed-off-by: Arnaldo Carvalho de Melo <[hidden email]>
> (cherry picked from commit b9b77222d4ff6b5bb8f5d87fca20de0910618bb9)
> Signed-off-by: Manoj Iyer <[hidden email]>
Acked-by: Stefan Bader <[hidden email]>
> ---
Looks to be safely out of the way of most things...

>  .../arm64/cavium/thunderx2/core-imp-def.json  | 87 ++++++++++++++++++-
>  1 file changed, 84 insertions(+), 3 deletions(-)
>
> diff --git a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
> index bc03c06c3918..752e47eb6977 100644
> --- a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
> +++ b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
> @@ -11,6 +11,21 @@
>      {
>          "ArchStdEvent": "L1D_CACHE_REFILL_WR",
>      },
> +    {
> +        "ArchStdEvent": "L1D_CACHE_REFILL_INNER",
> +    },
> +    {
> +        "ArchStdEvent": "L1D_CACHE_REFILL_OUTER",
> +    },
> +    {
> +        "ArchStdEvent": "L1D_CACHE_WB_VICTIM",
> +    },
> +    {
> +        "ArchStdEvent": "L1D_CACHE_WB_CLEAN",
> +    },
> +    {
> +        "ArchStdEvent": "L1D_CACHE_INVAL",
> +    },
>      {
>          "ArchStdEvent": "L1D_TLB_REFILL_RD",
>      },
> @@ -23,10 +38,76 @@
>      {
>          "ArchStdEvent": "L1D_TLB_WR",
>      },
> +    {
> +        "ArchStdEvent": "L2D_TLB_REFILL_RD",
> +    },
> +    {
> +        "ArchStdEvent": "L2D_TLB_REFILL_WR",
> +    },
> +    {
> +        "ArchStdEvent": "L2D_TLB_RD",
> +    },
> +    {
> +        "ArchStdEvent": "L2D_TLB_WR",
> +    },
>      {
>          "ArchStdEvent": "BUS_ACCESS_RD",
> -   },
> -   {
> +    },
> +    {
>          "ArchStdEvent": "BUS_ACCESS_WR",
> -   }
> +    },
> +    {
> +        "ArchStdEvent": "MEM_ACCESS_RD",
> +    },
> +    {
> +        "ArchStdEvent": "MEM_ACCESS_WR",
> +    },
> +    {
> +        "ArchStdEvent": "UNALIGNED_LD_SPEC",
> +    },
> +    {
> +        "ArchStdEvent": "UNALIGNED_ST_SPEC",
> +    },
> +    {
> +        "ArchStdEvent": "UNALIGNED_LDST_SPEC",
> +    },
> +    {
> +        "ArchStdEvent": "EXC_UNDEF",
> +    },
> +    {
> +        "ArchStdEvent": "EXC_SVC",
> +    },
> +    {
> +        "ArchStdEvent": "EXC_PABORT",
> +    },
> +    {
> +        "ArchStdEvent": "EXC_DABORT",
> +    },
> +    {
> +        "ArchStdEvent": "EXC_IRQ",
> +    },
> +    {
> +        "ArchStdEvent": "EXC_FIQ",
> +    },
> +    {
> +        "ArchStdEvent": "EXC_SMC",
> +    },
> +    {
> +        "ArchStdEvent": "EXC_HVC",
> +    },
> +    {
> +        "ArchStdEvent": "EXC_TRAP_PABORT",
> +    },
> +    {
> +        "ArchStdEvent": "EXC_TRAP_DABORT",
> +    },
> +    {
> +        "ArchStdEvent": "EXC_TRAP_OTHER",
> +    },
> +    {
> +        "ArchStdEvent": "EXC_TRAP_IRQ",
> +    },
> +    {
> +        "ArchStdEvent": "EXC_TRAP_FIQ",
> +    }
>  ]
>


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ACK: [PATCH] perf vendor events arm64: Update ThunderX2 implementation defined pmu core events

Kleber Souza
In reply to this post by Manoj Iyer
On 10/09/18 16:52, Manoj Iyer wrote:

> From: Ganapatrao Kulkarni <[hidden email]>
>
> BugLink: http://launchpad.net/bugs/1796904
>
> Signed-off-by: Ganapatrao Kulkarni <[hidden email]>
> Cc: Alexander Shishkin <[hidden email]>
> Cc: Ganapatrao Kulkarni <[hidden email]>
> Cc: Jan Glauber <[hidden email]>
> Cc: Jayachandran C <[hidden email]>
> Cc: Jiri Olsa <[hidden email]>
> Cc: [hidden email]
> Cc: Mark Rutland <[hidden email]>
> Cc: Namhyung Kim <[hidden email]>
> Cc: Peter Zijlstra <[hidden email]>
> Cc: Robert Richter <[hidden email]>
> Cc: Vadim Lomovtsev <[hidden email]>
> Cc: Will Deacon <[hidden email]>
> Link: http://lkml.kernel.org/r/20180731100251.23575-1-ganapatrao.kulkarni@...
> Signed-off-by: Arnaldo Carvalho de Melo <[hidden email]>
> (cherry picked from commit b9b77222d4ff6b5bb8f5d87fca20de0910618bb9)
> Signed-off-by: Manoj Iyer <[hidden email]>

Acked-by: Kleber Sacilotto de Souza <[hidden email]>

> ---
>  .../arm64/cavium/thunderx2/core-imp-def.json  | 87 ++++++++++++++++++-
>  1 file changed, 84 insertions(+), 3 deletions(-)
>
> diff --git a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
> index bc03c06c3918..752e47eb6977 100644
> --- a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
> +++ b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
> @@ -11,6 +11,21 @@
>      {
>          "ArchStdEvent": "L1D_CACHE_REFILL_WR",
>      },
> +    {
> +        "ArchStdEvent": "L1D_CACHE_REFILL_INNER",
> +    },
> +    {
> +        "ArchStdEvent": "L1D_CACHE_REFILL_OUTER",
> +    },
> +    {
> +        "ArchStdEvent": "L1D_CACHE_WB_VICTIM",
> +    },
> +    {
> +        "ArchStdEvent": "L1D_CACHE_WB_CLEAN",
> +    },
> +    {
> +        "ArchStdEvent": "L1D_CACHE_INVAL",
> +    },
>      {
>          "ArchStdEvent": "L1D_TLB_REFILL_RD",
>      },
> @@ -23,10 +38,76 @@
>      {
>          "ArchStdEvent": "L1D_TLB_WR",
>      },
> +    {
> +        "ArchStdEvent": "L2D_TLB_REFILL_RD",
> +    },
> +    {
> +        "ArchStdEvent": "L2D_TLB_REFILL_WR",
> +    },
> +    {
> +        "ArchStdEvent": "L2D_TLB_RD",
> +    },
> +    {
> +        "ArchStdEvent": "L2D_TLB_WR",
> +    },
>      {
>          "ArchStdEvent": "BUS_ACCESS_RD",
> -   },
> -   {
> +    },
> +    {
>          "ArchStdEvent": "BUS_ACCESS_WR",
> -   }
> +    },
> +    {
> +        "ArchStdEvent": "MEM_ACCESS_RD",
> +    },
> +    {
> +        "ArchStdEvent": "MEM_ACCESS_WR",
> +    },
> +    {
> +        "ArchStdEvent": "UNALIGNED_LD_SPEC",
> +    },
> +    {
> +        "ArchStdEvent": "UNALIGNED_ST_SPEC",
> +    },
> +    {
> +        "ArchStdEvent": "UNALIGNED_LDST_SPEC",
> +    },
> +    {
> +        "ArchStdEvent": "EXC_UNDEF",
> +    },
> +    {
> +        "ArchStdEvent": "EXC_SVC",
> +    },
> +    {
> +        "ArchStdEvent": "EXC_PABORT",
> +    },
> +    {
> +        "ArchStdEvent": "EXC_DABORT",
> +    },
> +    {
> +        "ArchStdEvent": "EXC_IRQ",
> +    },
> +    {
> +        "ArchStdEvent": "EXC_FIQ",
> +    },
> +    {
> +        "ArchStdEvent": "EXC_SMC",
> +    },
> +    {
> +        "ArchStdEvent": "EXC_HVC",
> +    },
> +    {
> +        "ArchStdEvent": "EXC_TRAP_PABORT",
> +    },
> +    {
> +        "ArchStdEvent": "EXC_TRAP_DABORT",
> +    },
> +    {
> +        "ArchStdEvent": "EXC_TRAP_OTHER",
> +    },
> +    {
> +        "ArchStdEvent": "EXC_TRAP_IRQ",
> +    },
> +    {
> +        "ArchStdEvent": "EXC_TRAP_FIQ",
> +    }
>  ]
>


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