[Zesty] [PATCH 0/2] nvme: Enable autonomous power state transitions

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[Zesty] [PATCH 0/2] nvme: Enable autonomous power state transitions

Kai-Heng Feng
BugLink: //bugs.launchpad.net/bugs/1664602

Impact:
NVME APST feature is not enabled, so the power consumption is higher.

Fix:
Enable NVME APST to converve energy.

Test:
Use 'nvme get-feature -f 0x0c -H /dev/nvme0' from nvme-cli to query the feature.

Before APST enabled:
get-feature:0xc (Autonomous Power State Transition), Current value:00000000
        Autonomous Power State Transition Enable (APSTE): Disabled

After APST enabled:
get-feature:0xc (Autonomous Power State Transition), Current value:0x000001
        Autonomous Power State Transition Enable (APSTE): Enabled

Commit 'bd4da3abaabf nvme: Add a quirk mechanism that uses identify_ctrl' cannot
be cleanly cherry-picked, it's contextually depends on another commit.
There's no functional dependency though, hence it's safe to backport the commit.

Andy Lutomirski (2):
  nvme: Add a quirk mechanism that uses identify_ctrl
  nvme: Enable autonomous power state transitions

 drivers/nvme/host/core.c | 218 +++++++++++++++++++++++++++++++++++++++++++++++
 drivers/nvme/host/nvme.h |  12 +++
 include/linux/nvme.h     |   6 ++
 3 files changed, 236 insertions(+)

--
2.12.0


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[PATCH 1/2] nvme: Add a quirk mechanism that uses identify_ctrl

Kai-Heng Feng
From: Andy Lutomirski <[hidden email]>

BugLink: https://bugs.launchpad.net/bugs/1664602

Currently, all NVMe quirks are based on PCI IDs.  Add a mechanism to
define quirks based on identify_ctrl's vendor id, model number,
and/or firmware revision.

Reviewed-by: Christoph Hellwig <[hidden email]>
Signed-off-by: Andy Lutomirski <[hidden email]>
Signed-off-by: Sagi Grimberg <[hidden email]>
Signed-off-by: Jens Axboe <[hidden email]>
(backported from commit bd4da3abaabffdd2472fb7085fcadd5d1d8c2153)
Signed-off-by: Kai-Heng Feng <[hidden email]>
---
 drivers/nvme/host/core.c | 64 ++++++++++++++++++++++++++++++++++++++++++++++++
 drivers/nvme/host/nvme.h |  1 +
 2 files changed, 65 insertions(+)

diff --git a/drivers/nvme/host/core.c b/drivers/nvme/host/core.c
index 8a3c3e32a704..d393d64955cb 100644
--- a/drivers/nvme/host/core.c
+++ b/drivers/nvme/host/core.c
@@ -1196,6 +1196,50 @@ static void nvme_set_queue_limits(struct nvme_ctrl *ctrl,
  blk_queue_write_cache(q, vwc, vwc);
 }
 
+struct nvme_core_quirk_entry {
+ /*
+ * NVMe model and firmware strings are padded with spaces.  For
+ * simplicity, strings in the quirk table are padded with NULLs
+ * instead.
+ */
+ u16 vid;
+ const char *mn;
+ const char *fr;
+ unsigned long quirks;
+};
+
+static const struct nvme_core_quirk_entry core_quirks[] = {
+};
+
+/* match is null-terminated but idstr is space-padded. */
+static bool string_matches(const char *idstr, const char *match, size_t len)
+{
+ size_t matchlen;
+
+ if (!match)
+ return true;
+
+ matchlen = strlen(match);
+ WARN_ON_ONCE(matchlen > len);
+
+ if (memcmp(idstr, match, matchlen))
+ return false;
+
+ for (; matchlen < len; matchlen++)
+ if (idstr[matchlen] != ' ')
+ return false;
+
+ return true;
+}
+
+static bool quirk_matches(const struct nvme_id_ctrl *id,
+  const struct nvme_core_quirk_entry *q)
+{
+ return q->vid == le16_to_cpu(id->vid) &&
+ string_matches(id->mn, q->mn, sizeof(id->mn)) &&
+ string_matches(id->fr, q->fr, sizeof(id->fr));
+}
+
 /*
  * Initialize the cached copies of the Identify data and various controller
  * register in our nvme_ctrl structure.  This should be called as soon as
@@ -1230,6 +1274,24 @@ int nvme_init_identify(struct nvme_ctrl *ctrl)
  return -EIO;
  }
 
+ if (!ctrl->identified) {
+ /*
+ * Check for quirks.  Quirk can depend on firmware version,
+ * so, in principle, the set of quirks present can change
+ * across a reset.  As a possible future enhancement, we
+ * could re-scan for quirks every time we reinitialize
+ * the device, but we'd have to make sure that the driver
+ * behaves intelligently if the quirks change.
+ */
+
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(core_quirks); i++) {
+ if (quirk_matches(id, &core_quirks[i]))
+ ctrl->quirks |= core_quirks[i].quirks;
+ }
+ }
+
  ctrl->vid = le16_to_cpu(id->vid);
  ctrl->oncs = le16_to_cpup(&id->oncs);
  atomic_set(&ctrl->abort_limit, id->acl + 1);
@@ -1272,6 +1334,8 @@ int nvme_init_identify(struct nvme_ctrl *ctrl)
  }
 
  kfree(id);
+
+ ctrl->identified = true;
  return ret;
 }
 EXPORT_SYMBOL_GPL(nvme_init_identify);
diff --git a/drivers/nvme/host/nvme.h b/drivers/nvme/host/nvme.h
index aead6d08ed2c..9dccf7127cce 100644
--- a/drivers/nvme/host/nvme.h
+++ b/drivers/nvme/host/nvme.h
@@ -111,6 +111,7 @@ enum nvme_ctrl_state {
 
 struct nvme_ctrl {
  enum nvme_ctrl_state state;
+ bool identified;
  spinlock_t lock;
  const struct nvme_ctrl_ops *ops;
  struct request_queue *admin_q;
--
2.12.0


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[PATCH 2/2] nvme: Enable autonomous power state transitions

Kai-Heng Feng
In reply to this post by Kai-Heng Feng
From: Andy Lutomirski <[hidden email]>

BugLink: https://bugs.launchpad.net/bugs/1664602

NVMe devices can advertise multiple power states.  These states can
be either "operational" (the device is fully functional but possibly
slow) or "non-operational" (the device is asleep until woken up).
Some devices can automatically enter a non-operational state when
idle for a specified amount of time and then automatically wake back
up when needed.

The hardware configuration is a table.  For each state, an entry in
the table indicates the next deeper non-operational state, if any,
to autonomously transition to and the idle time required before
transitioning.

This patch teaches the driver to program APST so that each successive
non-operational state will be entered after an idle time equal to 100%
of the total latency (entry plus exit) associated with that state.
The maximum acceptable latency is controlled using dev_pm_qos
(e.g. power/pm_qos_latency_tolerance_us in sysfs); non-operational
states with total latency greater than this value will not be used.
As a special case, setting the latency tolerance to 0 will disable
APST entirely.  On hardware without APST support, the sysfs file will
not be exposed.

The latency tolerance for newly-probed devices is set by the module
parameter nvme_core.default_ps_max_latency_us.

In theory, the device can expose "default" APST table, but this
doesn't seem to function correctly on my device (Samsung 950), nor
does it seem particularly useful.  There is also an optional
mechanism by which a configuration can be "saved" so it will be
automatically loaded on reset.  This can be configured from
userspace, but it doesn't seem useful to support in the driver.

On my laptop, enabling APST seems to save nearly 1W.

The hardware tables can be decoded in userspace with nvme-cli.
'nvme id-ctrl /dev/nvmeN' will show the power state table and
'nvme get-feature -f 0x0c -H /dev/nvme0' will show the current APST
configuration.

This feature is quirked off on a known-buggy Samsung device.

Signed-off-by: Andy Lutomirski <[hidden email]>
Reviewed-by: Christoph Hellwig <[hidden email]>
Signed-off-by: Sagi Grimberg <[hidden email]>
Signed-off-by: Jens Axboe <[hidden email]>
(cherry picked from commit c5552fde102fcc3f2cf9e502b8ac90e3500d8fdf)
Signed-off-by: Kai-Heng Feng <[hidden email]>
---
 drivers/nvme/host/core.c | 154 +++++++++++++++++++++++++++++++++++++++++++++++
 drivers/nvme/host/nvme.h |  11 ++++
 include/linux/nvme.h     |   6 ++
 3 files changed, 171 insertions(+)

diff --git a/drivers/nvme/host/core.c b/drivers/nvme/host/core.c
index d393d64955cb..344a4a7fdfdd 100644
--- a/drivers/nvme/host/core.c
+++ b/drivers/nvme/host/core.c
@@ -26,6 +26,7 @@
 #include <linux/ptrace.h>
 #include <linux/nvme_ioctl.h>
 #include <linux/t10-pi.h>
+#include <linux/pm_qos.h>
 #include <scsi/sg.h>
 #include <asm/unaligned.h>
 
@@ -56,6 +57,11 @@ EXPORT_SYMBOL_GPL(nvme_max_retries);
 static int nvme_char_major;
 module_param(nvme_char_major, int, 0);
 
+static unsigned long default_ps_max_latency_us = 25000;
+module_param(default_ps_max_latency_us, ulong, 0644);
+MODULE_PARM_DESC(default_ps_max_latency_us,
+ "max power saving latency for new devices; use PM QOS to change per device");
+
 static LIST_HEAD(nvme_ctrl_list);
 static DEFINE_SPINLOCK(dev_list_lock);
 
@@ -1196,6 +1202,122 @@ static void nvme_set_queue_limits(struct nvme_ctrl *ctrl,
  blk_queue_write_cache(q, vwc, vwc);
 }
 
+static void nvme_configure_apst(struct nvme_ctrl *ctrl)
+{
+ /*
+ * APST (Autonomous Power State Transition) lets us program a
+ * table of power state transitions that the controller will
+ * perform automatically.  We configure it with a simple
+ * heuristic: we are willing to spend at most 2% of the time
+ * transitioning between power states.  Therefore, when running
+ * in any given state, we will enter the next lower-power
+ * non-operational state after waiting 100 * (enlat + exlat)
+ * microseconds, as long as that state's total latency is under
+ * the requested maximum latency.
+ *
+ * We will not autonomously enter any non-operational state for
+ * which the total latency exceeds ps_max_latency_us.  Users
+ * can set ps_max_latency_us to zero to turn off APST.
+ */
+
+ unsigned apste;
+ struct nvme_feat_auto_pst *table;
+ int ret;
+
+ /*
+ * If APST isn't supported or if we haven't been initialized yet,
+ * then don't do anything.
+ */
+ if (!ctrl->apsta)
+ return;
+
+ if (ctrl->npss > 31) {
+ dev_warn(ctrl->device, "NPSS is invalid; not using APST\n");
+ return;
+ }
+
+ table = kzalloc(sizeof(*table), GFP_KERNEL);
+ if (!table)
+ return;
+
+ if (ctrl->ps_max_latency_us == 0) {
+ /* Turn off APST. */
+ apste = 0;
+ } else {
+ __le64 target = cpu_to_le64(0);
+ int state;
+
+ /*
+ * Walk through all states from lowest- to highest-power.
+ * According to the spec, lower-numbered states use more
+ * power.  NPSS, despite the name, is the index of the
+ * lowest-power state, not the number of states.
+ */
+ for (state = (int)ctrl->npss; state >= 0; state--) {
+ u64 total_latency_us, transition_ms;
+
+ if (target)
+ table->entries[state] = target;
+
+ /*
+ * Is this state a useful non-operational state for
+ * higher-power states to autonomously transition to?
+ */
+ if (!(ctrl->psd[state].flags &
+      NVME_PS_FLAGS_NON_OP_STATE))
+ continue;
+
+ total_latency_us =
+ (u64)le32_to_cpu(ctrl->psd[state].entry_lat) +
+ + le32_to_cpu(ctrl->psd[state].exit_lat);
+ if (total_latency_us > ctrl->ps_max_latency_us)
+ continue;
+
+ /*
+ * This state is good.  Use it as the APST idle
+ * target for higher power states.
+ */
+ transition_ms = total_latency_us + 19;
+ do_div(transition_ms, 20);
+ if (transition_ms > (1 << 24) - 1)
+ transition_ms = (1 << 24) - 1;
+
+ target = cpu_to_le64((state << 3) |
+     (transition_ms << 8));
+ }
+
+ apste = 1;
+ }
+
+ ret = nvme_set_features(ctrl, NVME_FEAT_AUTO_PST, apste,
+ table, sizeof(*table), NULL);
+ if (ret)
+ dev_err(ctrl->device, "failed to set APST feature (%d)\n", ret);
+
+ kfree(table);
+}
+
+static void nvme_set_latency_tolerance(struct device *dev, s32 val)
+{
+ struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
+ u64 latency;
+
+ switch (val) {
+ case PM_QOS_LATENCY_TOLERANCE_NO_CONSTRAINT:
+ case PM_QOS_LATENCY_ANY:
+ latency = U64_MAX;
+ break;
+
+ default:
+ latency = val;
+ }
+
+ if (ctrl->ps_max_latency_us != latency) {
+ ctrl->ps_max_latency_us = latency;
+ nvme_configure_apst(ctrl);
+ }
+}
+
 struct nvme_core_quirk_entry {
  /*
  * NVMe model and firmware strings are padded with spaces.  For
@@ -1209,6 +1331,16 @@ struct nvme_core_quirk_entry {
 };
 
 static const struct nvme_core_quirk_entry core_quirks[] = {
+ /*
+ * Seen on a Samsung "SM951 NVMe SAMSUNG 256GB": using APST causes
+ * the controller to go out to lunch.  It dies when the watchdog
+ * timer reads CSTS and gets 0xffffffff.
+ */
+ {
+ .vid = 0x144d,
+ .fr = "BXW75D0Q",
+ .quirks = NVME_QUIRK_NO_APST,
+ },
 };
 
 /* match is null-terminated but idstr is space-padded. */
@@ -1251,6 +1383,7 @@ int nvme_init_identify(struct nvme_ctrl *ctrl)
  u64 cap;
  int ret, page_shift;
  u32 max_hw_sectors;
+ u8 prev_apsta;
 
  ret = ctrl->ops->reg_read32(ctrl, NVME_REG_VS, &ctrl->vs);
  if (ret) {
@@ -1311,6 +1444,11 @@ int nvme_init_identify(struct nvme_ctrl *ctrl)
  ctrl->sgls = le32_to_cpu(id->sgls);
  ctrl->kas = le16_to_cpu(id->kas);
 
+ ctrl->npss = id->npss;
+ prev_apsta = ctrl->apsta;
+ ctrl->apsta = (ctrl->quirks & NVME_QUIRK_NO_APST) ? 0 : id->apsta;
+ memcpy(ctrl->psd, id->psd, sizeof(ctrl->psd));
+
  if (ctrl->ops->is_fabrics) {
  ctrl->icdoff = le16_to_cpu(id->icdoff);
  ctrl->ioccsz = le32_to_cpu(id->ioccsz);
@@ -1335,7 +1473,15 @@ int nvme_init_identify(struct nvme_ctrl *ctrl)
 
  kfree(id);
 
+ if (ctrl->apsta && !prev_apsta)
+ dev_pm_qos_expose_latency_tolerance(ctrl->device);
+ else if (!ctrl->apsta && prev_apsta)
+ dev_pm_qos_hide_latency_tolerance(ctrl->device);
+
+ nvme_configure_apst(ctrl);
+
  ctrl->identified = true;
+
  return ret;
 }
 EXPORT_SYMBOL_GPL(nvme_init_identify);
@@ -2073,6 +2219,14 @@ int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev,
  list_add_tail(&ctrl->node, &nvme_ctrl_list);
  spin_unlock(&dev_list_lock);
 
+ /*
+ * Initialize latency tolerance controls.  The sysfs files won't
+ * be visible to userspace unless the device actually supports APST.
+ */
+ ctrl->device->power.set_latency_tolerance = nvme_set_latency_tolerance;
+ dev_pm_qos_update_user_latency_tolerance(ctrl->device,
+ min(default_ps_max_latency_us, (unsigned long)S32_MAX));
+
  return 0;
 out_release_instance:
  nvme_release_instance(ctrl);
diff --git a/drivers/nvme/host/nvme.h b/drivers/nvme/host/nvme.h
index 9dccf7127cce..590fc00fcb79 100644
--- a/drivers/nvme/host/nvme.h
+++ b/drivers/nvme/host/nvme.h
@@ -77,6 +77,11 @@ enum nvme_quirks {
  * readiness, which is done by reading the NVME_CSTS_RDY bit.
  */
  NVME_QUIRK_DELAY_BEFORE_CHK_RDY = (1 << 3),
+
+ /*
+ * APST should not be used.
+ */
+ NVME_QUIRK_NO_APST = (1 << 4),
 };
 
 /*
@@ -144,13 +149,19 @@ struct nvme_ctrl {
  u32 vs;
  u32 sgls;
  u16 kas;
+ u8 npss;
+ u8 apsta;
  unsigned int kato;
  bool subsystem;
  unsigned long quirks;
+ struct nvme_id_power_state psd[32];
  struct work_struct scan_work;
  struct work_struct async_event_work;
  struct delayed_work ka_work;
 
+ /* Power saving configuration */
+ u64 ps_max_latency_us;
+
  /* Fabrics only */
  u16 sqsize;
  u32 ioccsz;
diff --git a/include/linux/nvme.h b/include/linux/nvme.h
index 614176124cea..6540cf82f168 100644
--- a/include/linux/nvme.h
+++ b/include/linux/nvme.h
@@ -576,6 +576,12 @@ struct nvme_write_zeroes_cmd {
  __le16 appmask;
 };
 
+/* Features */
+
+struct nvme_feat_auto_pst {
+ __le64 entries[32];
+};
+
 /* Admin commands */
 
 enum nvme_admin_opcode {
--
2.12.0


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APPLIED: [Zesty] [PATCH 0/2] nvme: Enable autonomous power state transitions

Tim Gardner-2
In reply to this post by Kai-Heng Feng
Positive test results
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