[bionic][PATCH 00/59] drm/i915: Add support for Cannonlake (CNL)

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[bionic][PATCH 00/59] drm/i915: Add support for Cannonlake (CNL)

Timo Aaltonen-6
BugLink: http://bugs.launchpad.net/bugs/1757573

This backport adds support for Cannonlake to bionic/4.15, based on a list
of commits provided by Intel. Most of the patches were straight cherry-picks,
a handful needed slight adjustments to fit. 25 patches are from drm-intel-next-queued
-branch which will be mainlined in 4.17, the rest are from 4.16.


Anusha Srivatsa (2):
  drm/i915/cnl: Update the DMC version on CNL
  drm/i915/dmc: DMC 1.07 for Cannonlake

Chris Wilson (3):
  drm/i915: Unify SLICE_UNIT_LEVEL_CLKGATE w/a for cnl
  drm/i915/execlists: Listen to COMPLETE context event not ACTIVE_IDLE
  drm/i915: Track GGTT writes on the vma

David Weinehall (1):
  drm/i915: Don't use GEN6_RC_VIDEO_FREQ on gen10+

James Ausmus (1):
  drm/i915/glk: Refactor handling of PLANE_COLOR_CTL for GLK+

Jani Nikula (4):
  drm/i915/bios: add DP max link rate to VBT child device struct
  drm/i915/dp: abstract rate array length limiting
  drm/i915/dp: clean up source rate limiting for cnl
  drm/i915/dp: limit DP link rate based on VBT on CNL+

Joonas Lahtinen (1):
  drm/i915/cnl: Add support for horizontal plane flipping

Lucas De Marchi (1):
  drm/i915/cnl: apply Display WA #1178 to fix type C dongles

Mahesh Kumar (1):
  drm/i915/cnl: Fix PORT_TX_DW5/7 register address

Michel Thierry (2):
  drm/i915/cnl: Remove unnecessary check in cnl_setup_private_ppat
  drm/i915/execlists: Delay writing to ELSP until HW has processed the
    previous write

Mika Kahola (1):
  drm/i915/cnl: Symmetric scalers for each pipe

Mika Kuoppala (1):
  drm/i915: Use fallback forcewake if primary ack missing

Rafael Antognolli (4):
  drm/i915: Implement ReadHitWriteOnlyDisable.
  drm/i915: Implement WaDisableVFclkgate.
  drm/i915: Implement WaDisableEarlyEOT.
  drm/i915/cnl: WaPipeControlBefore3DStateSamplePattern

Rodrigo Vivi (29):
  drm/i915/cnp: Ignore VBT request for know invalid DDC pin.
  drm/i915/cnp: Properly handle VBT ddc pin out of bounds.
  drm/i915/cnl: Force DDI_A_4_LANES when needed.
  drm/i915/cnl: Get RC6 working.
  drm/i915/cnl: Allow 2 pixel per clock on Cannonlake.
  drm/i915/cnl: Fix SSEU Device Status.
  drm/i915: Display WA #1185 WaDisableDARBFClkGating:cnl, glk
  drm/i915/cnl: Remove spurious central_freq.
  drm/i915/cnl: Remove useless conversion.
  drm/i915/cnl: Fix, simplify and unify wrpll variable sizes.
  drm/i915/cnl: Fix wrpll math for higher freqs.
  drm/i915/cnl: Don't blindly replace qdiv.
  drm/i915/cnl: Simplify dco_fraction calculation.
  drm/i915/cnl: Extend HDMI 2.0 support to CNL.
  drm/i915/cnl: Add Port F definition.
  drm/i915/cnl: Fix aux selection for WA 1178
  drm/i915/cnl: Add Cannonlake PCI IDs for another SKU.
  drm/i915/cnl: Add AUX-F support
  drm/i915/cnl: Extend Wa 1178 to Aux F.
  drm/i915/cnl: Fix _CNL_PORT_TX_DW2_LN0_F definition.
  drm/i915: Fix DPLCLKA_CFGCR0 bits for Port F.
  drm/i915/cnl: Add right GMBUS pin number for HDMI on Port F.
  drm/i915: For HPD connected port use hpd_pin instead of port.
  drm/i915/cnl: Add HPD support for Port F.
  drm/i915/cnl: Enable DDI-F on Cannonlake.
  drm/i915/cnl: Fix DP max rate for Cannonlake with port F.
  drm/i915/cnl: Sync PCI ID with Spec.
  drm/i915/cnl: Add WaRsDisableCoarsePowerGating
  drm/i915/cnl: Remove alpha_support protection

Tvrtko Ursulin (2):
  drm/i915: Restore GT performance in headless mode with DMC loaded
  drm/i915: Apply headless DMC workaround for CNL

Ville Syrjälä (6):
  drm/i915: Clean up some cdclk switch statements
  drm/i915: Start tracking voltage level in the cdclk state
  drm/i915: Use cdclk_state->voltage on CNL
  drm/i915: Adjust system agent voltage on CNL if required by DDI ports
  drm/i915: Sanity check cdclk in vlv_set_cdclk()
  drm/i915: Perform a central cdclk state sanity check

 drivers/gpu/drm/i915/i915_debugfs.c      |  61 +++++++-
 drivers/gpu/drm/i915/i915_drv.h          |  25 +++-
 drivers/gpu/drm/i915/i915_gem.c          |  61 +++++---
 drivers/gpu/drm/i915/i915_gem_gtt.c      |   6 -
 drivers/gpu/drm/i915/i915_gem_request.c  |  14 ++
 drivers/gpu/drm/i915/i915_irq.c          |  41 ++++--
 drivers/gpu/drm/i915/i915_pci.c          |   6 +-
 drivers/gpu/drm/i915/i915_reg.h          |  72 +++++++--
 drivers/gpu/drm/i915/i915_vma.c          |  22 +++
 drivers/gpu/drm/i915/i915_vma.h          |  19 +++
 drivers/gpu/drm/i915/intel_bios.c        |  50 ++++++-
 drivers/gpu/drm/i915/intel_cdclk.c       | 240 ++++++++++++++++++++----------
 drivers/gpu/drm/i915/intel_csr.c         |   5 +-
 drivers/gpu/drm/i915/intel_ddi.c         |  61 ++++++--
 drivers/gpu/drm/i915/intel_device_info.c |   5 +-
 drivers/gpu/drm/i915/intel_display.c     | 170 ++++++++++++++++-----
 drivers/gpu/drm/i915/intel_dp.c          | 245 ++++++++++++++++++-------------
 drivers/gpu/drm/i915/intel_dp_mst.c      |   5 +
 drivers/gpu/drm/i915/intel_dpll_mgr.c    |  63 ++++----
 drivers/gpu/drm/i915/intel_drv.h         |  21 ++-
 drivers/gpu/drm/i915/intel_engine_cs.c   |   3 +
 drivers/gpu/drm/i915/intel_guc.c         |   2 +-
 drivers/gpu/drm/i915/intel_hdmi.c        |  12 +-
 drivers/gpu/drm/i915/intel_hotplug.c     |  19 ++-
 drivers/gpu/drm/i915/intel_lrc.c         |  64 +++++++-
 drivers/gpu/drm/i915/intel_lspcon.c      |   3 +-
 drivers/gpu/drm/i915/intel_pm.c          |  41 ++++--
 drivers/gpu/drm/i915/intel_ringbuffer.h  |   1 +
 drivers/gpu/drm/i915/intel_runtime_pm.c  |  54 ++++++-
 drivers/gpu/drm/i915/intel_sprite.c      |  11 +-
 drivers/gpu/drm/i915/intel_uncore.c      | 137 +++++++++++++++--
 drivers/gpu/drm/i915/intel_vbt_defs.h    |   9 ++
 include/drm/i915_component.h             |   3 +-
 include/drm/i915_pciids.h                |  27 ++--
 34 files changed, 1186 insertions(+), 392 deletions(-)

--
2.15.1


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[PATCH 01/59] drm/i915/cnp: Ignore VBT request for know invalid DDC pin.

Timo Aaltonen-6
From: Rodrigo Vivi <[hidden email]>

BugLink: http://bugs.launchpad.net/bugs/1757573

Let's ignore VBT request if the pin is clearly wrong.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104139
Cc: Kai Heng Feng <[hidden email]>
Signed-off-by: Rodrigo Vivi <[hidden email]>
Link: https://patchwork.freedesktop.org/patch/msgid/20180123174050.4261-1-rodrigo.vivi@...
Reviewed-by: Radhakrishna Sripada <[hidden email]>
(cherry picked from commit a8e6f3888b05c1e7b685800a3371ce050720368f)
Signed-off-by: Timo Aaltonen <[hidden email]>
---
 drivers/gpu/drm/i915/intel_bios.c | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 1fa3ebbf2dce..8ad56c275ff0 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -1116,9 +1116,14 @@ static const u8 cnp_ddc_pin_map[] = {
 
 static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
 {
- if (HAS_PCH_CNP(dev_priv) &&
-    vbt_pin > 0 && vbt_pin < ARRAY_SIZE(cnp_ddc_pin_map))
- return cnp_ddc_pin_map[vbt_pin];
+ if (HAS_PCH_CNP(dev_priv)) {
+ if (vbt_pin > 0 && vbt_pin < ARRAY_SIZE(cnp_ddc_pin_map))
+ return cnp_ddc_pin_map[vbt_pin];
+ if (vbt_pin > GMBUS_PIN_4_CNP) {
+ DRM_DEBUG_KMS("Ignoring alternate pin: VBT claims DDC pin %d, which is not valid for this platform\n", vbt_pin);
+ return 0;
+ }
+ }
 
  return vbt_pin;
 }
--
2.15.1


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[PATCH 02/59] drm/i915/cnp: Properly handle VBT ddc pin out of bounds.

Timo Aaltonen-6
In reply to this post by Timo Aaltonen-6
From: Rodrigo Vivi <[hidden email]>

BugLink: http://bugs.launchpad.net/bugs/1757573

If the table result is out of bounds on the array map
there is something really wrong with VBT pin so we don't
return that vbt_pin, but only return 0 instead.

This basically reverts commit 'a8e6f3888b05 ("drm/i915/cnp:
Ignore VBT request for know invalid DDC pin.")'

Also this properly fixes commit 9c3b2689d01f ("drm/i915/cnl:
Map VBT DDC Pin to BSpec DDC Pin.")

v2: Do in a way that we don't break other platforms. (Jani)

v3: Keep debug message (Jani)

v4: Don't mess with 0 mapping was noticed by Jani and
    addressed with a simple solution suggested by Lucas
    that makes this even simpler.

Fixes: a8e6f3888b05 ("drm/i915/cnp: Ignore VBT request for know invalid DDC pin.")
Fixes: 9c3b2689d01f ("drm/i915/cnl: Map VBT DDC Pin to BSpec DDC Pin.")
Cc: Radhakrishna Sripada <[hidden email]>
Cc: Jani Nikula <[hidden email]>
Cc: Kai Heng Feng <[hidden email]>
Cc: Lucas De Marchi <[hidden email]>
Suggested-by: Lucas De Marchi <[hidden email]>
Signed-off-by: Rodrigo Vivi <[hidden email]>
Reviewed-by: Lucas De Marchi <[hidden email]>
Tested-by: Kai-Heng Feng <[hidden email]>
Link: https://patchwork.freedesktop.org/patch/msgid/20180125222524.22059-1-rodrigo.vivi@...
(cherry picked from commit 3393ce1ed8fc43dbdb83952facaf04e644ca1d54)
Signed-off-by: Timo Aaltonen <[hidden email]>
---
 drivers/gpu/drm/i915/intel_bios.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 8ad56c275ff0..10cc39d2173c 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -1108,6 +1108,7 @@ static void sanitize_aux_ch(struct drm_i915_private *dev_priv,
 }
 
 static const u8 cnp_ddc_pin_map[] = {
+ [0] = 0, /* N/A */
  [DDC_BUS_DDI_B] = GMBUS_PIN_1_BXT,
  [DDC_BUS_DDI_C] = GMBUS_PIN_2_BXT,
  [DDC_BUS_DDI_D] = GMBUS_PIN_4_CNP, /* sic */
@@ -1117,9 +1118,9 @@ static const u8 cnp_ddc_pin_map[] = {
 static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
 {
  if (HAS_PCH_CNP(dev_priv)) {
- if (vbt_pin > 0 && vbt_pin < ARRAY_SIZE(cnp_ddc_pin_map))
+ if (vbt_pin < ARRAY_SIZE(cnp_ddc_pin_map)) {
  return cnp_ddc_pin_map[vbt_pin];
- if (vbt_pin > GMBUS_PIN_4_CNP) {
+ } else {
  DRM_DEBUG_KMS("Ignoring alternate pin: VBT claims DDC pin %d, which is not valid for this platform\n", vbt_pin);
  return 0;
  }
--
2.15.1


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[PATCH 03/59] drm/i915/cnl: Force DDI_A_4_LANES when needed.

Timo Aaltonen-6
In reply to this post by Timo Aaltonen-6
From: Rodrigo Vivi <[hidden email]>

BugLink: http://bugs.launchpad.net/bugs/1757573

As we faced in BXT, on CNL DDI_A_4_LANES is not
set as expected when system is boot with multiple
monitors connected. This result in wrong lane
setup impacting the max data rate available and
consequently blocking modeset on eDP, resulting
in a blank screen.

Most of CNL SKUs don't support DDI-E.
The only SKU that supports DDI-E is the same
that supports the full A/E split called DDI-F.

Also when DDI-F is used DDI-E cannot be used because
they share Interrupts. So DDI-E is almost useless.
Anyways let's consider this is possible and rely on
VBT for that.

This patch was initialy start by Clint, but required
many changes including full commit message. So
Credits entirely to Clint for finding this.

v2: Extract all messy conditions into a helper function
    as suggested by Ville.
    Along with simplification I removed the debug
    message on the working case since now all conditions
    are grouped.
v3: Split the conditions even more as suggested by Ville.
    Get's cleaner and easier to add new cases in the
    future.

Suggested-by: Clint Taylor <[hidden email]>
Cc: Clint Taylor <[hidden email]>
Cc: Mika Kahola <[hidden email]>
Cc: Jani Nikula <[hidden email]>
Cc: Ville Syrjälä <[hidden email]>
Signed-off-by: Rodrigo Vivi <[hidden email]>
Reviewed-by: Ville Syrjälä <[hidden email]>
Link: https://patchwork.freedesktop.org/patch/msgid/20171023173920.22890-1-rodrigo.vivi@...
(cherry picked from commit 436009b578ab872619350a4c4f2b36c98c7e55a2)
Signed-off-by: Timo Aaltonen <[hidden email]>
---
 drivers/gpu/drm/i915/intel_ddi.c | 46 ++++++++++++++++++++++++++++++----------
 1 file changed, 35 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 58a3755544b2..b3b50ae1790d 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2716,6 +2716,34 @@ intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
  return connector;
 }
 
+static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport)
+{
+ struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
+
+ if (dport->port != PORT_A)
+ return false;
+
+ if (dport->saved_port_bits & DDI_A_4_LANES)
+ return false;
+
+ /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
+ *                     supported configuration
+ */
+ if (IS_GEN9_LP(dev_priv))
+ return true;
+
+ /* Cannonlake: Most of SKUs don't support DDI_E, and the only
+ *             one who does also have a full A/E split called
+ *             DDI_F what makes DDI_E useless. However for this
+ *             case let's trust VBT info.
+ */
+ if (IS_CANNONLAKE(dev_priv) &&
+    !intel_bios_is_port_present(dev_priv, PORT_E))
+ return true;
+
+ return false;
+}
+
 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
 {
  struct intel_digital_port *intel_dig_port;
@@ -2825,18 +2853,14 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
  }
 
  /*
- * Bspec says that DDI_A_4_LANES is the only supported configuration
- * for Broxton.  Yet some BIOS fail to set this bit on port A if eDP
- * wasn't lit up at boot.  Force this bit on in our internal
- * configuration so that we use the proper lane count for our
- * calculations.
+ * Some BIOS might fail to set this bit on port A if eDP
+ * wasn't lit up at boot.  Force this bit set when needed
+ * so we use the proper lane count for our calculations.
  */
- if (IS_GEN9_LP(dev_priv) && port == PORT_A) {
- if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
- DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
- intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
- max_lanes = 4;
- }
+ if (intel_ddi_a_force_4_lanes(intel_dig_port)) {
+ DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n");
+ intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
+ max_lanes = 4;
  }
 
  intel_dig_port->max_lanes = max_lanes;
--
2.15.1


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[PATCH 04/59] drm/i915/cnl: Get RC6 working.

Timo Aaltonen-6
In reply to this post by Timo Aaltonen-6
From: Rodrigo Vivi <[hidden email]>

BugLink: http://bugs.launchpad.net/bugs/1757573

On CNL, individual wake rate limit was added to each engine.

GT can only go to RC6 if both Render and Media engines are
individually qualified. So we need to set their individual
wake rate limit.

+-----------------+---------------+--------------+--------------+
|                 |    GT RC6     |  Render C6   |   Media C6   |
+-----------------+---------------+--------------+--------------+
| Wake rate limit | 0xA09C[31:16] | 0xA09C[15:0] | 0xA0A0[15:0] |
+-----------------+---------------+--------------+--------------+

v2: - Tune Render and Media wake rate values according to some extra
      info I got from HW engineers. Value can be tuned, but for now
      these are the recommended values.
    - Fix typos pointed by James.

Cc: Nathan Ciobanu <[hidden email]>
Cc: Wayne Boyer <[hidden email]>
Cc: Joe Konno <[hidden email]>
Cc: David Weinehall <[hidden email]>
Signed-off-by: Rodrigo Vivi <[hidden email]>
Reviewed-by: James Ausmus <[hidden email]>
Reviewed-by: David Weinehall <[hidden email]>
Link: https://patchwork.freedesktop.org/patch/msgid/20171023224612.27208-1-rodrigo.vivi@...
(cherry picked from commit 0aab201b4ad10fa530e4d12f8ea30b6f0a0540bd)
Signed-off-by: Timo Aaltonen <[hidden email]>
---
 drivers/gpu/drm/i915/i915_reg.h |  1 +
 drivers/gpu/drm/i915/intel_pm.c | 15 +++++++++++----
 2 files changed, 12 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7923dfd9963c..861b29f57c09 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7905,6 +7905,7 @@ enum {
 #define GEN6_RC1_WAKE_RATE_LIMIT _MMIO(0xA098)
 #define GEN6_RC6_WAKE_RATE_LIMIT _MMIO(0xA09C)
 #define GEN6_RC6pp_WAKE_RATE_LIMIT _MMIO(0xA0A0)
+#define GEN10_MEDIA_WAKE_RATE_LIMIT _MMIO(0xA0A0)
 #define GEN6_RC_EVALUATION_INTERVAL _MMIO(0xA0A8)
 #define GEN6_RC_IDLE_HYSTERSIS _MMIO(0xA0AC)
 #define GEN6_RC_SLEEP _MMIO(0xA0B0)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f0d0dbab4150..b68d444b1791 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6614,12 +6614,19 @@ static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
  I915_WRITE(GEN6_RC_CONTROL, 0);
 
  /* 2b: Program RC6 thresholds.*/
-
- /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
- if (IS_SKYLAKE(dev_priv))
+ if (INTEL_GEN(dev_priv) >= 10) {
+ I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
+ I915_WRITE(GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
+ } else if (IS_SKYLAKE(dev_priv)) {
+ /*
+ * WaRsDoubleRc6WrlWithCoarsePowerGating:skl Doubling WRL only
+ * when CPG is enabled
+ */
  I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
- else
+ } else {
  I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
+ }
+
  I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
  I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
  for_each_engine(engine, dev_priv, id)
--
2.15.1


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[PATCH 05/59] drm/i915/cnl: Update the DMC version on CNL

Timo Aaltonen-6
In reply to this post by Timo Aaltonen-6
From: Anusha Srivatsa <[hidden email]>

BugLink: http://bugs.launchpad.net/bugs/1757573

The latest version of DMC on CNL is 1.06.
Update the version so as to load the
latest firmware.

Release Notes:
Version: 1.06
1. DDI and AUX IO related fix.

v2: Improve the prefixes in commit message.
Add Release Notes directly. (Rodrigo)

Cc: Rodrigo Vivi <[hidden email]>
Signed-off-by: Anusha Srivatsa <[hidden email]>
Reviewed-by: Rodrigo Vivi <[hidden email]>
Signed-off-by: Rodrigo Vivi <[hidden email]>
Link: https://patchwork.freedesktop.org/patch/msgid/1507053588-677-1-git-send-email-anusha.srivatsa@...
(cherry picked from commit b40c88fda1300b2dd65fcc3377d54b724edf47e6)
Signed-off-by: Timo Aaltonen <[hidden email]>
---
 drivers/gpu/drm/i915/intel_csr.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index da9de47562b8..3e1f86d0c6cc 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -37,8 +37,8 @@
 #define I915_CSR_GLK "i915/glk_dmc_ver1_04.bin"
 #define GLK_CSR_VERSION_REQUIRED CSR_VERSION(1, 4)
 
-#define I915_CSR_CNL "i915/cnl_dmc_ver1_04.bin"
-#define CNL_CSR_VERSION_REQUIRED CSR_VERSION(1, 4)
+#define I915_CSR_CNL "i915/cnl_dmc_ver1_06.bin"
+#define CNL_CSR_VERSION_REQUIRED CSR_VERSION(1, 6)
 
 #define I915_CSR_KBL "i915/kbl_dmc_ver1_01.bin"
 MODULE_FIRMWARE(I915_CSR_KBL);
--
2.15.1


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[PATCH 06/59] drm/i915: Clean up some cdclk switch statements

Timo Aaltonen-6
In reply to this post by Timo Aaltonen-6
From: Ville Syrjälä <[hidden email]>

BugLink: http://bugs.launchpad.net/bugs/1757573

Redo some switch statements in the cdclk code to use a common
fall through for the default case. Makes everything look a bit
more uniform

Cc: Mika Kahola <[hidden email]>
Cc: Manasi Navare <[hidden email]>
Cc: Rodrigo Vivi <[hidden email]>
Signed-off-by: Ville Syrjälä <[hidden email]>
Reviewed-by: Mika Kahola <[hidden email]>
Link: https://patchwork.freedesktop.org/patch/msgid/20171024095216.1638-2-ville.syrjala@...
(cherry picked from commit 2b58417ffbca9fafa1d54b9f1272965f98f456ca)
Signed-off-by: Timo Aaltonen <[hidden email]>
---
 drivers/gpu/drm/i915/intel_cdclk.c | 68 +++++++++++++++++++-------------------
 1 file changed, 34 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index 60cf4e58389a..d8a4b523d878 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -681,6 +681,13 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
  val &= ~LCPLL_CLK_FREQ_MASK;
 
  switch (cdclk) {
+ default:
+ MISSING_CASE(cdclk);
+ /* fall through */
+ case 337500:
+ val |= LCPLL_CLK_FREQ_337_5_BDW;
+ data = 2;
+ break;
  case 450000:
  val |= LCPLL_CLK_FREQ_450;
  data = 0;
@@ -689,17 +696,10 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
  val |= LCPLL_CLK_FREQ_54O_BDW;
  data = 1;
  break;
- case 337500:
- val |= LCPLL_CLK_FREQ_337_5_BDW;
- data = 2;
- break;
  case 675000:
  val |= LCPLL_CLK_FREQ_675_BDW;
  data = 3;
  break;
- default:
- WARN(1, "invalid cdclk frequency\n");
- return;
  }
 
  I915_WRITE(LCPLL_CTL, val);
@@ -920,8 +920,6 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
  u32 freq_select, pcu_ack, cdclk_ctl;
  int ret;
 
- WARN_ON((cdclk == 24000) != (vco == 0));
-
  mutex_lock(&dev_priv->pcu_lock);
  ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
  SKL_CDCLK_PREPARE_FOR_CHANGE,
@@ -936,6 +934,15 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
 
  /* Choose frequency for this cdclk */
  switch (cdclk) {
+ default:
+ WARN_ON(cdclk != dev_priv->cdclk.hw.ref);
+ WARN_ON(vco != 0);
+ /* fall through */
+ case 308571:
+ case 337500:
+ freq_select = CDCLK_FREQ_337_308;
+ pcu_ack = 0;
+ break;
  case 450000:
  case 432000:
  freq_select = CDCLK_FREQ_450_432;
@@ -945,12 +952,6 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
  freq_select = CDCLK_FREQ_540;
  pcu_ack = 2;
  break;
- case 308571:
- case 337500:
- default:
- freq_select = CDCLK_FREQ_337_308;
- pcu_ack = 0;
- break;
  case 617143:
  case 675000:
  freq_select = CDCLK_FREQ_675_617;
@@ -1127,6 +1128,7 @@ static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
  switch (cdclk) {
  default:
  MISSING_CASE(cdclk);
+ /* fall through */
  case 144000:
  case 288000:
  case 384000:
@@ -1151,6 +1153,7 @@ static int glk_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
  switch (cdclk) {
  default:
  MISSING_CASE(cdclk);
+ /* fall through */
  case  79200:
  case 158400:
  case 316800:
@@ -1263,24 +1266,22 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
 
  /* cdclk = vco / 2 / div{1,1.5,2,4} */
  switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
- case 8:
- divider = BXT_CDCLK_CD2X_DIV_SEL_4;
- break;
- case 4:
- divider = BXT_CDCLK_CD2X_DIV_SEL_2;
+ default:
+ WARN_ON(cdclk != dev_priv->cdclk.hw.ref);
+ WARN_ON(vco != 0);
+ /* fall through */
+ case 2:
+ divider = BXT_CDCLK_CD2X_DIV_SEL_1;
  break;
  case 3:
  WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
  divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
  break;
- case 2:
- divider = BXT_CDCLK_CD2X_DIV_SEL_1;
+ case 4:
+ divider = BXT_CDCLK_CD2X_DIV_SEL_2;
  break;
- default:
- WARN_ON(cdclk != dev_priv->cdclk.hw.ref);
- WARN_ON(vco != 0);
-
- divider = BXT_CDCLK_CD2X_DIV_SEL_1;
+ case 8:
+ divider = BXT_CDCLK_CD2X_DIV_SEL_4;
  break;
  }
 
@@ -1549,18 +1550,16 @@ static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
 
  /* cdclk = vco / 2 / div{1,2} */
  switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
- case 4:
- divider = BXT_CDCLK_CD2X_DIV_SEL_2;
- break;
- case 2:
- divider = BXT_CDCLK_CD2X_DIV_SEL_1;
- break;
  default:
  WARN_ON(cdclk != dev_priv->cdclk.hw.ref);
  WARN_ON(vco != 0);
-
+ /* fall through */
+ case 2:
  divider = BXT_CDCLK_CD2X_DIV_SEL_1;
  break;
+ case 4:
+ divider = BXT_CDCLK_CD2X_DIV_SEL_2;
+ break;
  }
 
  switch (cdclk) {
@@ -1609,6 +1608,7 @@ static int cnl_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
  switch (cdclk) {
  default:
  MISSING_CASE(cdclk);
+ /* fall through */
  case 168000:
  case 336000:
  ratio = dev_priv->cdclk.hw.ref == 19200 ? 35 : 28;
--
2.15.1


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[PATCH 07/59] drm/i915: Start tracking voltage level in the cdclk state

Timo Aaltonen-6
In reply to this post by Timo Aaltonen-6
From: Ville Syrjälä <[hidden email]>

BugLink: http://bugs.launchpad.net/bugs/1757573

For CNL we'll need to start considering the port clocks when we select
the voltage level for the system agent. To that end start tracking the
voltage in the cdclk state (since that already has to adjust it).

v2: s/voltage/voltage_level/ (Rodrigo)

Cc: Mika Kahola <[hidden email]>
Cc: Manasi Navare <[hidden email]>
Cc: Rodrigo Vivi <[hidden email]>
Signed-off-by: Ville Syrjälä <[hidden email]>
Reviewed-by: Rodrigo Vivi <[hidden email]>
Link: https://patchwork.freedesktop.org/patch/msgid/20171024095216.1638-3-ville.syrjala@...
(cherry picked from commit 64600bd5b8280208dfbd33bcd7a5f32255058f07)
Signed-off-by: Timo Aaltonen <[hidden email]>
---
 drivers/gpu/drm/i915/i915_drv.h         |  1 +
 drivers/gpu/drm/i915/intel_cdclk.c      | 31 ++++++++++++++++++++++++-------
 drivers/gpu/drm/i915/intel_display.c    |  8 ++++----
 drivers/gpu/drm/i915/intel_drv.h        |  4 +++-
 drivers/gpu/drm/i915/intel_runtime_pm.c |  3 ++-
 5 files changed, 34 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3eb899bbb7aa..2d618865b3dd 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2228,6 +2228,7 @@ struct i915_oa_ops {
 
 struct intel_cdclk_state {
  unsigned int cdclk, vco, ref;
+ u8 voltage_level;
 };
 
 struct drm_i915_private {
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index d8a4b523d878..e8b4e19e978b 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1707,17 +1707,34 @@ void cnl_uninit_cdclk(struct drm_i915_private *dev_priv)
 }
 
 /**
- * intel_cdclk_state_compare - Determine if two CDCLK states differ
+ * intel_cdclk_needs_modeset - Determine if two CDCLK states require a modeset on all pipes
  * @a: first CDCLK state
  * @b: second CDCLK state
  *
  * Returns:
- * True if the CDCLK states are identical, false if they differ.
+ * True if the CDCLK states require pipes to be off during reprogramming, false if not.
  */
-bool intel_cdclk_state_compare(const struct intel_cdclk_state *a,
+bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
        const struct intel_cdclk_state *b)
 {
- return memcmp(a, b, sizeof(*a)) == 0;
+ return a->cdclk != b->cdclk ||
+ a->vco != b->vco ||
+ a->ref != b->ref;
+}
+
+/**
+ * intel_cdclk_changed - Determine if two CDCLK states are different
+ * @a: first CDCLK state
+ * @b: second CDCLK state
+ *
+ * Returns:
+ * True if the CDCLK states don't match, false if they do.
+ */
+bool intel_cdclk_changed(const struct intel_cdclk_state *a,
+ const struct intel_cdclk_state *b)
+{
+ return intel_cdclk_needs_modeset(a, b) ||
+ a->voltage_level != b->voltage_level;
 }
 
 /**
@@ -1731,15 +1748,15 @@ bool intel_cdclk_state_compare(const struct intel_cdclk_state *a,
 void intel_set_cdclk(struct drm_i915_private *dev_priv,
      const struct intel_cdclk_state *cdclk_state)
 {
- if (intel_cdclk_state_compare(&dev_priv->cdclk.hw, cdclk_state))
+ if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state))
  return;
 
  if (WARN_ON_ONCE(!dev_priv->display.set_cdclk))
  return;
 
- DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz, VCO %d kHz, ref %d kHz\n",
+ DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz, VCO %d kHz, ref %d kHz, voltage_level %d\n",
  cdclk_state->cdclk, cdclk_state->vco,
- cdclk_state->ref);
+ cdclk_state->ref, cdclk_state->voltage_level);
 
  dev_priv->display.set_cdclk(dev_priv, cdclk_state);
 }
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a83e18c72f7b..c6ca73479f6f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11956,16 +11956,16 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
  * holding all the crtc locks, even if we don't end up
  * touching the hardware
  */
- if (!intel_cdclk_state_compare(&dev_priv->cdclk.logical,
-       &intel_state->cdclk.logical)) {
+ if (intel_cdclk_changed(&dev_priv->cdclk.logical,
+ &intel_state->cdclk.logical)) {
  ret = intel_lock_all_pipes(state);
  if (ret < 0)
  return ret;
  }
 
  /* All pipes must be switched off while we change the cdclk. */
- if (!intel_cdclk_state_compare(&dev_priv->cdclk.actual,
-       &intel_state->cdclk.actual)) {
+ if (intel_cdclk_needs_modeset(&dev_priv->cdclk.actual,
+      &intel_state->cdclk.actual)) {
  ret = intel_modeset_all_pipes(state);
  if (ret < 0)
  return ret;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 5d77f75a9f9c..94c193961824 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1323,8 +1323,10 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
 void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
 void intel_update_cdclk(struct drm_i915_private *dev_priv);
 void intel_update_rawclk(struct drm_i915_private *dev_priv);
-bool intel_cdclk_state_compare(const struct intel_cdclk_state *a,
+bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
        const struct intel_cdclk_state *b);
+bool intel_cdclk_changed(const struct intel_cdclk_state *a,
+ const struct intel_cdclk_state *b);
 void intel_set_cdclk(struct drm_i915_private *dev_priv,
      const struct intel_cdclk_state *cdclk_state);
 
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index d169bfb98368..01cd705f605b 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -715,7 +715,8 @@ static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
  gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 
  dev_priv->display.get_cdclk(dev_priv, &cdclk_state);
- WARN_ON(!intel_cdclk_state_compare(&dev_priv->cdclk.hw, &cdclk_state));
+ /* Can't read out voltage_level so can't use intel_cdclk_changed() */
+ WARN_ON(intel_cdclk_needs_modeset(&dev_priv->cdclk.hw, &cdclk_state));
 
  gen9_assert_dbuf_enabled(dev_priv);
 
--
2.15.1


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[PATCH 08/59] drm/i915: Use cdclk_state->voltage on CNL

Timo Aaltonen-6
In reply to this post by Timo Aaltonen-6
From: Ville Syrjälä <[hidden email]>

BugLink: http://bugs.launchpad.net/bugs/1757573

Track the system agent voltage we request from pcode in the cdclk state
on CNL. Annoyingly we can't actually read out the current value since
there's no pcode command to do that, so we'll have to just assume that
it worked.

v2: s/voltage/voltage_level/ (Rodrigo)

Cc: Mika Kahola <[hidden email]>
Cc: Manasi Navare <[hidden email]>
Cc: Rodrigo Vivi <[hidden email]>
Signed-off-by: Ville Syrjälä <[hidden email]>
Reviewed-by: Rodrigo Vivi <[hidden email]>
Link: https://patchwork.freedesktop.org/patch/msgid/20171024095216.1638-8-ville.syrjala@...
(cherry picked from commit 48469eced282155608a80a37626d28a0abd3c2e5)
Signed-off-by: Timo Aaltonen <[hidden email]>
---
 drivers/gpu/drm/i915/intel_cdclk.c | 47 +++++++++++++++++++++++++-------------
 1 file changed, 31 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index e8b4e19e978b..519fef55d342 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1443,6 +1443,19 @@ static int cnl_calc_cdclk(int min_cdclk)
  return 168000;
 }
 
+static u8 cnl_calc_voltage_level(int cdclk)
+{
+ switch (cdclk) {
+ default:
+ case 168000:
+ return 0;
+ case 336000:
+ return 1;
+ case 528000:
+ return 2;
+ }
+}
+
 static void cnl_cdclk_pll_update(struct drm_i915_private *dev_priv,
  struct intel_cdclk_state *cdclk_state)
 {
@@ -1476,7 +1489,7 @@ static void cnl_get_cdclk(struct drm_i915_private *dev_priv,
  cdclk_state->cdclk = cdclk_state->ref;
 
  if (cdclk_state->vco == 0)
- return;
+ goto out;
 
  divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
 
@@ -1493,6 +1506,14 @@ static void cnl_get_cdclk(struct drm_i915_private *dev_priv,
  }
 
  cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
+
+ out:
+ /*
+ * Can't read this out :( Let's assume it's
+ * at least what the CDCLK frequency requires.
+ */
+ cdclk_state->voltage_level =
+ cnl_calc_voltage_level(cdclk_state->cdclk);
 }
 
 static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
@@ -1533,7 +1554,7 @@ static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
 {
  int cdclk = cdclk_state->cdclk;
  int vco = cdclk_state->vco;
- u32 val, divider, pcu_ack;
+ u32 val, divider;
  int ret;
 
  mutex_lock(&dev_priv->pcu_lock);
@@ -1562,19 +1583,6 @@ static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
  break;
  }
 
- switch (cdclk) {
- case 528000:
- pcu_ack = 2;
- break;
- case 336000:
- pcu_ack = 1;
- break;
- case 168000:
- default:
- pcu_ack = 0;
- break;
- }
-
  if (dev_priv->cdclk.hw.vco != 0 &&
     dev_priv->cdclk.hw.vco != vco)
  cnl_cdclk_pll_disable(dev_priv);
@@ -1592,7 +1600,8 @@ static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
 
  /* inform PCU of the change */
  mutex_lock(&dev_priv->pcu_lock);
- sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
+ sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
+ cdclk_state->voltage_level);
  mutex_unlock(&dev_priv->pcu_lock);
 
  intel_update_cdclk(dev_priv);
@@ -1685,6 +1694,7 @@ void cnl_init_cdclk(struct drm_i915_private *dev_priv)
 
  cdclk_state.cdclk = cnl_calc_cdclk(0);
  cdclk_state.vco = cnl_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
+ cdclk_state.voltage_level = cnl_calc_voltage_level(cdclk_state.cdclk);
 
  cnl_set_cdclk(dev_priv, &cdclk_state);
 }
@@ -1702,6 +1712,7 @@ void cnl_uninit_cdclk(struct drm_i915_private *dev_priv)
 
  cdclk_state.cdclk = cdclk_state.ref;
  cdclk_state.vco = 0;
+ cdclk_state.voltage_level = cnl_calc_voltage_level(cdclk_state.cdclk);
 
  cnl_set_cdclk(dev_priv, &cdclk_state);
 }
@@ -2009,6 +2020,8 @@ static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
 
  intel_state->cdclk.logical.vco = vco;
  intel_state->cdclk.logical.cdclk = cdclk;
+ intel_state->cdclk.logical.voltage_level =
+ cnl_calc_voltage_level(cdclk);
 
  if (!intel_state->active_crtcs) {
  cdclk = cnl_calc_cdclk(0);
@@ -2016,6 +2029,8 @@ static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
 
  intel_state->cdclk.actual.vco = vco;
  intel_state->cdclk.actual.cdclk = cdclk;
+ intel_state->cdclk.actual.voltage_level =
+ cnl_calc_voltage_level(cdclk);
  } else {
  intel_state->cdclk.actual =
  intel_state->cdclk.logical;
--
2.15.1


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[PATCH 09/59] drm/i915: Adjust system agent voltage on CNL if required by DDI ports

Timo Aaltonen-6
In reply to this post by Timo Aaltonen-6
From: Ville Syrjälä <[hidden email]>

BugLink: http://bugs.launchpad.net/bugs/1757573

On CNL we may need to bump up the system agent voltage not only due
to CDCLK but also when driving DDI port with a sufficiently high clock.
To that end start tracking the minimum acceptable voltage for each crtc.
We do the tracking via crtcs because we don't have any kind of encoder
state. Also there's no downside to doing it this way, and it matches how
we track cdclk requirements on account of pixel rate.

v2: Allow disabled crtcs to use the min voltage
    Add IS_CNL check to intel_ddi_compute_min_voltage() since
    we're using CNL specific values there
    s/intel_compute_min_voltage/cnl_compute_min_voltage/ since
    the function makes hw specific assumptions about the voltage
    values
v3: Drop the test hack leftovers from skl_modeset_calc_cdclk()
v4: s/voltage/voltage_level/ (Rodrigo)
    Replace DPLL DVFS FIXMEs with an explanation why we don't
    do anything there (Rodrigo)

Cc: Mika Kahola <[hidden email]>
Cc: Manasi Navare <[hidden email]>
Cc: Rodrigo Vivi <[hidden email]>
Signed-off-by: Ville Syrjälä <[hidden email]>
Reviewed-by: Rodrigo Vivi <[hidden email]>
Link: https://patchwork.freedesktop.org/patch/msgid/20171024095216.1638-9-ville.syrjala@...
(cherry picked from commit 53e9bf5e8159765e0dc807567180afd0b389f149)
Signed-off-by: Timo Aaltonen <[hidden email]>
---
 drivers/gpu/drm/i915/i915_drv.h       |  2 ++
 drivers/gpu/drm/i915/intel_cdclk.c    | 46 ++++++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_ddi.c      | 11 +++++++++
 drivers/gpu/drm/i915/intel_display.c  | 11 +++++++++
 drivers/gpu/drm/i915/intel_dp_mst.c   |  5 ++++
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 16 ++++++------
 drivers/gpu/drm/i915/intel_drv.h      |  7 ++++++
 7 files changed, 89 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2d618865b3dd..4458b74b16c0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2419,6 +2419,8 @@ struct drm_i915_private {
  unsigned int active_crtcs;
  /* minimum acceptable cdclk for each pipe */
  int min_cdclk[I915_MAX_PIPES];
+ /* minimum acceptable voltage level for each pipe */
+ u8 min_voltage_level[I915_MAX_PIPES];
 
  int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
 
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index 519fef55d342..663f08ddc0bc 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1605,6 +1605,12 @@ static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
  mutex_unlock(&dev_priv->pcu_lock);
 
  intel_update_cdclk(dev_priv);
+
+ /*
+ * Can't read out the voltage level :(
+ * Let's just assume everything is as expected.
+ */
+ dev_priv->cdclk.hw.voltage_level = cdclk_state->voltage_level;
 }
 
 static int cnl_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
@@ -1874,6 +1880,43 @@ static int intel_compute_min_cdclk(struct drm_atomic_state *state)
  return min_cdclk;
 }
 
+/*
+ * Note that this functions assumes that 0 is
+ * the lowest voltage value, and higher values
+ * correspond to increasingly higher voltages.
+ *
+ * Should that relationship no longer hold on
+ * future platforms this code will need to be
+ * adjusted.
+ */
+static u8 cnl_compute_min_voltage_level(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_crtc *crtc;
+ struct intel_crtc_state *crtc_state;
+ u8 min_voltage_level;
+ int i;
+ enum pipe pipe;
+
+ memcpy(state->min_voltage_level, dev_priv->min_voltage_level,
+       sizeof(state->min_voltage_level));
+
+ for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
+ if (crtc_state->base.enable)
+ state->min_voltage_level[i] =
+ crtc_state->min_voltage_level;
+ else
+ state->min_voltage_level[i] = 0;
+ }
+
+ min_voltage_level = 0;
+ for_each_pipe(dev_priv, pipe)
+ min_voltage_level = max(state->min_voltage_level[pipe],
+ min_voltage_level);
+
+ return min_voltage_level;
+}
+
 static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state)
 {
  struct drm_i915_private *dev_priv = to_i915(state->dev);
@@ -2021,7 +2064,8 @@ static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
  intel_state->cdclk.logical.vco = vco;
  intel_state->cdclk.logical.cdclk = cdclk;
  intel_state->cdclk.logical.voltage_level =
- cnl_calc_voltage_level(cdclk);
+ max(cnl_calc_voltage_level(cdclk),
+    cnl_compute_min_voltage_level(intel_state));
 
  if (!intel_state->active_crtcs) {
  cdclk = cnl_calc_cdclk(0);
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index b3b50ae1790d..25baf7d3bb73 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2547,6 +2547,13 @@ bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
  return false;
 }
 
+void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
+ struct intel_crtc_state *crtc_state)
+{
+ if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
+ crtc_state->min_voltage_level = 2;
+}
+
 void intel_ddi_get_config(struct intel_encoder *encoder,
   struct intel_crtc_state *pipe_config)
 {
@@ -2646,6 +2653,8 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
  if (IS_GEN9_LP(dev_priv))
  pipe_config->lane_lat_optim_mask =
  bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
+
+ intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
 }
 
 static bool intel_ddi_compute_config(struct intel_encoder *encoder,
@@ -2672,6 +2681,8 @@ static bool intel_ddi_compute_config(struct intel_encoder *encoder,
  bxt_ddi_phy_calc_lane_lat_optim_mask(encoder,
      pipe_config->lane_count);
 
+ intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
+
  return ret;
 
 }
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c6ca73479f6f..ee62180736cd 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5925,6 +5925,7 @@ static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
 
  dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
  dev_priv->min_cdclk[intel_crtc->pipe] = 0;
+ dev_priv->min_voltage_level[intel_crtc->pipe] = 0;
 }
 
 /*
@@ -11314,6 +11315,8 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv,
  PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
  PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
 
+ PIPE_CONF_CHECK_I(min_voltage_level);
+
 #undef PIPE_CONF_CHECK_X
 #undef PIPE_CONF_CHECK_I
 #undef PIPE_CONF_CHECK_P
@@ -11974,6 +11977,9 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
  DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
       intel_state->cdclk.logical.cdclk,
       intel_state->cdclk.actual.cdclk);
+ DRM_DEBUG_KMS("New voltage level calculated to be logical %u, actual %u\n",
+      intel_state->cdclk.logical.voltage_level,
+      intel_state->cdclk.actual.voltage_level);
  } else {
  to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical;
  }
@@ -12542,6 +12548,9 @@ static int intel_atomic_commit(struct drm_device *dev,
  if (intel_state->modeset) {
  memcpy(dev_priv->min_cdclk, intel_state->min_cdclk,
        sizeof(intel_state->min_cdclk));
+ memcpy(dev_priv->min_voltage_level,
+       intel_state->min_voltage_level,
+       sizeof(intel_state->min_voltage_level));
  dev_priv->active_crtcs = intel_state->active_crtcs;
  dev_priv->cdclk.logical = intel_state->cdclk.logical;
  dev_priv->cdclk.actual = intel_state->cdclk.actual;
@@ -15061,6 +15070,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
  }
 
  dev_priv->min_cdclk[crtc->pipe] = min_cdclk;
+ dev_priv->min_voltage_level[crtc->pipe] =
+ crtc_state->min_voltage_level;
 
  intel_pipe_config_sanity_check(dev_priv, crtc_state);
  }
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
index 772521440a9f..3d62c63c0763 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -34,6 +34,7 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
  struct intel_crtc_state *pipe_config,
  struct drm_connector_state *conn_state)
 {
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
  struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base);
  struct intel_digital_port *intel_dig_port = intel_mst->primary;
  struct intel_dp *intel_dp = &intel_dig_port->dp;
@@ -87,6 +88,8 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
 
  pipe_config->dp_m_n.tu = slots;
 
+ intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
+
  return true;
 }
 
@@ -307,6 +310,8 @@ static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder,
  intel_dp_get_m_n(crtc, pipe_config);
 
  intel_ddi_clock_get(&intel_dig_port->base, pipe_config);
+
+ intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
 }
 
 static int intel_dp_mst_get_ddc_modes(struct drm_connector *connector)
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index df808a94c511..897fffe1ecd8 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2008,8 +2008,8 @@ static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv,
  * requirement, follow the Display Voltage Frequency Switching
  * Sequence Before Frequency Change
  *
- * FIXME: (DVFS) is used to adjust the display voltage to match the
- * display clock frequencies
+ * Note: DVFS is actually handled via the cdclk code paths,
+ * hence we do nothing here.
  */
 
  /* 6. Enable DPLL in DPLL_ENABLE. */
@@ -2030,8 +2030,8 @@ static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv,
  * requirement, follow the Display Voltage Frequency Switching
  * Sequence After Frequency Change
  *
- * FIXME: (DVFS) is used to adjust the display voltage to match the
- * display clock frequencies
+ * Note: DVFS is actually handled via the cdclk code paths,
+ * hence we do nothing here.
  */
 
  /*
@@ -2055,8 +2055,8 @@ static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv,
  * requirement, follow the Display Voltage Frequency Switching
  * Sequence Before Frequency Change
  *
- * FIXME: (DVFS) is used to adjust the display voltage to match the
- * display clock frequencies
+ * Note: DVFS is actually handled via the cdclk code paths,
+ * hence we do nothing here.
  */
 
  /* 3. Disable DPLL through DPLL_ENABLE. */
@@ -2077,8 +2077,8 @@ static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv,
  * requirement, follow the Display Voltage Frequency Switching
  * Sequence After Frequency Change
  *
- * FIXME: (DVFS) is used to adjust the display voltage to match the
- * display clock frequencies
+ * Note: DVFS is actually handled via the cdclk code paths,
+ * hence we do nothing here.
  */
 
  /* 6. Disable DPLL power in DPLL_ENABLE. */
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 94c193961824..1c6c378891f6 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -386,6 +386,8 @@ struct intel_atomic_state {
  unsigned int active_crtcs;
  /* minimum acceptable cdclk for each pipe */
  int min_cdclk[I915_MAX_PIPES];
+ /* minimum acceptable voltage level for each pipe */
+ u8 min_voltage_level[I915_MAX_PIPES];
 
  struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
 
@@ -738,6 +740,9 @@ struct intel_crtc_state {
  */
  uint8_t lane_lat_optim_mask;
 
+ /* minimum acceptable voltage level */
+ u8 min_voltage_level;
+
  /* Panel fitter controls for gen2-gen4 + VLV */
  struct {
  u32 control;
@@ -1293,6 +1298,8 @@ void intel_ddi_clock_get(struct intel_encoder *encoder,
  struct intel_crtc_state *pipe_config);
 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
     bool state);
+void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
+ struct intel_crtc_state *crtc_state);
 u32 bxt_signal_levels(struct intel_dp *intel_dp);
 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
--
2.15.1


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[PATCH 10/59] drm/i915: Sanity check cdclk in vlv_set_cdclk()

Timo Aaltonen-6
In reply to this post by Timo Aaltonen-6
From: Ville Syrjälä <[hidden email]>

BugLink: http://bugs.launchpad.net/bugs/1757573

chv_set_cdclk() sanity checks that the cdclk frequency is one of the
legal values. Do the same in the VLV function.

Cc: Mika Kahola <[hidden email]>
Cc: Manasi Navare <[hidden email]>
Cc: Rodrigo Vivi <[hidden email]>
Signed-off-by: Ville Syrjälä <[hidden email]>
Link: https://patchwork.freedesktop.org/patch/msgid/20171024095216.1638-10-ville.syrjala@...
Reviewed-by: Rodrigo Vivi <[hidden email]>
(cherry picked from commit 0c9f353f014e6d88a5af8b305503a5396fe63ff8)
Signed-off-by: Timo Aaltonen <[hidden email]>
---
 drivers/gpu/drm/i915/intel_cdclk.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index 663f08ddc0bc..68dcca8f1322 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -488,6 +488,18 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
  int cdclk = cdclk_state->cdclk;
  u32 val, cmd;
 
+ switch (cdclk) {
+ case 400000:
+ case 333333:
+ case 320000:
+ case 266667:
+ case 200000:
+ break;
+ default:
+ MISSING_CASE(cdclk);
+ return;
+ }
+
  /* There are cases where we can end up here with power domains
  * off and a CDCLK frequency other than the minimum, like when
  * issuing a modeset without actually changing any display after
--
2.15.1


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[PATCH 11/59] drm/i915: Perform a central cdclk state sanity check

Timo Aaltonen-6
In reply to this post by Timo Aaltonen-6
From: Ville Syrjälä <[hidden email]>

BugLink: http://bugs.launchpad.net/bugs/1757573

WARN if the cdclk state doesn't match what we expect after programming.
And let's remove the WARN from bdw_set_cdclk() that's trying to achieve
the same thing in a more limite fashion.

Also take the opportunity to refactor the code to use a common function
for dumping out a cdclk state.

Cc: Mika Kahola <[hidden email]>
Cc: Manasi Navare <[hidden email]>
Cc: Rodrigo Vivi <[hidden email]>
Signed-off-by: Ville Syrjälä <[hidden email]>
Link: https://patchwork.freedesktop.org/patch/msgid/20171024095216.1638-11-ville.syrjala@...
Reviewed-by: Rodrigo Vivi <[hidden email]>
(cherry picked from commit cfddadc98abc85f478c92187c944e0ee963f741b)
Signed-off-by: Timo Aaltonen <[hidden email]>
---
 drivers/gpu/drm/i915/intel_cdclk.c   | 30 +++++++++++++++++++-----------
 drivers/gpu/drm/i915/intel_display.c |  3 +++
 drivers/gpu/drm/i915/intel_drv.h     |  2 ++
 3 files changed, 24 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index 68dcca8f1322..59995c3bd87e 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -731,10 +731,6 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
  I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
 
  intel_update_cdclk(dev_priv);
-
- WARN(cdclk != dev_priv->cdclk.hw.cdclk,
-     "cdclk requested %d kHz but got %d kHz\n",
-     cdclk, dev_priv->cdclk.hw.cdclk);
 }
 
 static int skl_calc_cdclk(int min_cdclk, int vco)
@@ -1025,6 +1021,8 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
  goto sanitize;
 
  intel_update_cdclk(dev_priv);
+ intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
+
  /* Is PLL enabled and locked ? */
  if (dev_priv->cdclk.hw.vco == 0 ||
     dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
@@ -1349,6 +1347,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
  u32 cdctl, expected;
 
  intel_update_cdclk(dev_priv);
+ intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
 
  if (dev_priv->cdclk.hw.vco == 0 ||
     dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
@@ -1653,6 +1652,7 @@ static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv)
  u32 cdctl, expected;
 
  intel_update_cdclk(dev_priv);
+ intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
 
  if (dev_priv->cdclk.hw.vco == 0 ||
     dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
@@ -1766,6 +1766,14 @@ bool intel_cdclk_changed(const struct intel_cdclk_state *a,
  a->voltage_level != b->voltage_level;
 }
 
+void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
+    const char *context)
+{
+ DRM_DEBUG_DRIVER("%s %d kHz, VCO %d kHz, ref %d kHz, voltage level %d\n",
+ context, cdclk_state->cdclk, cdclk_state->vco,
+ cdclk_state->ref, cdclk_state->voltage_level);
+}
+
 /**
  * intel_set_cdclk - Push the CDCLK state to the hardware
  * @dev_priv: i915 device
@@ -1783,11 +1791,15 @@ void intel_set_cdclk(struct drm_i915_private *dev_priv,
  if (WARN_ON_ONCE(!dev_priv->display.set_cdclk))
  return;
 
- DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz, VCO %d kHz, ref %d kHz, voltage_level %d\n",
- cdclk_state->cdclk, cdclk_state->vco,
- cdclk_state->ref, cdclk_state->voltage_level);
+ intel_dump_cdclk_state(cdclk_state, "Changing CDCLK to");
 
  dev_priv->display.set_cdclk(dev_priv, cdclk_state);
+
+ if (WARN(intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state),
+ "cdclk state doesn't match!\n")) {
+ intel_dump_cdclk_state(&dev_priv->cdclk.hw, "[hw state]");
+ intel_dump_cdclk_state(cdclk_state, "[sw state]");
+ }
 }
 
 static int intel_pixel_rate_to_cdclk(struct drm_i915_private *dev_priv,
@@ -2204,10 +2216,6 @@ void intel_update_cdclk(struct drm_i915_private *dev_priv)
 {
  dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw);
 
- DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
- dev_priv->cdclk.hw.cdclk, dev_priv->cdclk.hw.vco,
- dev_priv->cdclk.hw.ref);
-
  /*
  * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
  * Programmng [sic] note: bit[9:2] should be programmed to the number
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ee62180736cd..a8aa802dfdb3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8844,7 +8844,9 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
  }
 
  intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
  intel_update_cdclk(dev_priv);
+ intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
 }
 
 /*
@@ -14393,6 +14395,7 @@ void intel_modeset_init_hw(struct drm_device *dev)
  struct drm_i915_private *dev_priv = to_i915(dev);
 
  intel_update_cdclk(dev_priv);
+ intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
  dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
 }
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 1c6c378891f6..ec1d5e96aaf6 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1336,6 +1336,8 @@ bool intel_cdclk_changed(const struct intel_cdclk_state *a,
  const struct intel_cdclk_state *b);
 void intel_set_cdclk(struct drm_i915_private *dev_priv,
      const struct intel_cdclk_state *cdclk_state);
+void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
+    const char *context);
 
 /* intel_display.c */
 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
--
2.15.1


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[PATCH 12/59] drm/i915/cnl: Allow 2 pixel per clock on Cannonlake.

Timo Aaltonen-6
In reply to this post by Timo Aaltonen-6
From: Rodrigo Vivi <[hidden email]>

BugLink: http://bugs.launchpad.net/bugs/1757573

This is heavily based on a initial patch provided by Ville
plus all changes provided later by Ander.

As Geminilake, Cannonlake also supports 2 pixels per clock.

Different from Geminilake we are not implementing the 99% Wa.
But we can revisit that decision later if we find out
any limitation on later CNL SKUs.

v2: Rebase on top of commit 'd305e0614601 ("drm/i915: Track
minimum acceptable cdclk instead of "minimum dotclock")'

v3: When fixing HDMI on CNL I noticed that I missed to convert
    back the doubled pixel rate to cdclk.

Cc: Paulo Zanoni <[hidden email]>
Cc: Ville Syrjälä <[hidden email]>
Cc: Dhinakaran Pandiyan <[hidden email]>
Cc: Jani Nikula <[hidden email]>
Signed-off-by: Rodrigo Vivi <[hidden email]>
Reviewed-by: Paulo Zanoni <[hidden email]>
Link: https://patchwork.freedesktop.org/patch/msgid/20171003223142.26264-1-rodrigo.vivi@...
(cherry picked from commit 43037c86d10cea185f6518f797f6303a06e734f9)
Signed-off-by: Timo Aaltonen <[hidden email]>
---
 drivers/gpu/drm/i915/intel_cdclk.c   | 14 ++------------
 drivers/gpu/drm/i915/intel_display.c |  2 +-
 drivers/gpu/drm/i915/intel_pm.c      |  3 ++-
 3 files changed, 5 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index 59995c3bd87e..9c2c94cb6add 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1806,12 +1806,7 @@ static int intel_pixel_rate_to_cdclk(struct drm_i915_private *dev_priv,
      int pixel_rate)
 {
  if (INTEL_GEN(dev_priv) >= 10)
- /*
- * FIXME: Switch to DIV_ROUND_UP(pixel_rate, 2)
- * once DDI clock voltage requirements are
- * handled correctly.
- */
- return pixel_rate;
+ return DIV_ROUND_UP(pixel_rate, 2);
  else if (IS_GEMINILAKE(dev_priv))
  /*
  * FIXME: Avoid using a pixel clock that is more than 99% of the cdclk
@@ -2112,12 +2107,7 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
  int max_cdclk_freq = dev_priv->max_cdclk_freq;
 
  if (INTEL_GEN(dev_priv) >= 10)
- /*
- * FIXME: Allow '2 * max_cdclk_freq'
- * once DDI clock voltage requirements are
- * handled correctly.
- */
- return max_cdclk_freq;
+ return 2 * max_cdclk_freq;
  else if (IS_GEMINILAKE(dev_priv))
  /*
  * FIXME: Limiting to 99% as a temporary workaround. See
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a8aa802dfdb3..0c516d48e7bc 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12794,7 +12794,7 @@ skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state
  crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
  max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
 
- if (IS_GEMINILAKE(dev_priv))
+ if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
  max_dotclk *= 2;
 
  if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b68d444b1791..5c5667fbdb3d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3924,6 +3924,7 @@ skl_pipe_downscale_amount(const struct intel_crtc_state *crtc_state)
 int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
   struct intel_crtc_state *cstate)
 {
+ struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
  struct drm_crtc_state *crtc_state = &cstate->base;
  struct drm_atomic_state *state = crtc_state->state;
  struct drm_plane *plane;
@@ -3966,7 +3967,7 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
  crtc_clock = crtc_state->adjusted_mode.crtc_clock;
  dotclk = to_intel_atomic_state(state)->cdclk.logical.cdclk;
 
- if (IS_GEMINILAKE(to_i915(intel_crtc->base.dev)))
+ if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
  dotclk *= 2;
 
  pipe_max_pixel_rate = div_round_up_u32_fixed16(dotclk, pipe_downscale);
--
2.15.1


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[PATCH 13/59] drm/i915/cnl: Fix SSEU Device Status.

Timo Aaltonen-6
In reply to this post by Timo Aaltonen-6
From: Rodrigo Vivi <[hidden email]>

BugLink: http://bugs.launchpad.net/bugs/1757573

CNL adds an extra register for slice/subslice information.
Although no SKU is planed with an extra slice let's already
handle this extra piece of information so we don't have the
risk in future of getting a part that might have chosen this
part of the die instead of other slices or anything like that.

Also if subslice is disabled the information of eu ack for that
is garbage, so let's skip checks for eu if subslice is disabled
as we skip the subslice if slice is disabled.

The rest is pretty much like gen9.

v2: Remove IS_CANNONLAKE from gen9 status function.

v3: Consider s_max = 6 and ss_max=4 to run over all possible
    slices and subslices possible by spec. Although no real
    hardware will have that many slices/subslices.
    To match with sseu info init.
v4: Fix offset calculation for slices 4 and 5.
    Removed Oscar's rv-b since this change also needs review.
v5: Let's consider only valid bits for SLICE*_PGCTL_ACK.
    This looks like wrong in Spec, but seems to be enough
    for now. Whenever Spec gets updated and fixed we come
    back and properly update the masks. Also add a FIXME,
    so we can revisit this later when we find some strange
    info on debugfs or when we noitce spec got updated.

Cc: Oscar Mateo <[hidden email]>
Signed-off-by: Rodrigo Vivi <[hidden email]>
Reviewed-by: Lionel Landwerlin <[hidden email]>
Link: https://patchwork.freedesktop.org/patch/msgid/20171026001546.28203-1-rodrigo.vivi@...
(cherry picked from commit f8c3dcf946bfb1e0519fb095d02f9b7def30a749)
Signed-off-by: Timo Aaltonen <[hidden email]>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 61 +++++++++++++++++++++++++++++++++++--
 drivers/gpu/drm/i915/i915_reg.h     |  7 +++++
 2 files changed, 66 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index c65e381b85f3..34862aa8f9c0 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4448,6 +4448,61 @@ static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
  }
 }
 
+static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
+     struct sseu_dev_info *sseu)
+{
+ const struct intel_device_info *info = INTEL_INFO(dev_priv);
+ int s_max = 6, ss_max = 4;
+ int s, ss;
+ u32 s_reg[s_max], eu_reg[2 * s_max], eu_mask[2];
+
+ for (s = 0; s < s_max; s++) {
+ /*
+ * FIXME: Valid SS Mask respects the spec and read
+ * only valid bits for those registers, excluding reserverd
+ * although this seems wrong because it would leave many
+ * subslices without ACK.
+ */
+ s_reg[s] = I915_READ(GEN10_SLICE_PGCTL_ACK(s)) &
+ GEN10_PGCTL_VALID_SS_MASK(s);
+ eu_reg[2 * s] = I915_READ(GEN10_SS01_EU_PGCTL_ACK(s));
+ eu_reg[2 * s + 1] = I915_READ(GEN10_SS23_EU_PGCTL_ACK(s));
+ }
+
+ eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
+     GEN9_PGCTL_SSA_EU19_ACK |
+     GEN9_PGCTL_SSA_EU210_ACK |
+     GEN9_PGCTL_SSA_EU311_ACK;
+ eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
+     GEN9_PGCTL_SSB_EU19_ACK |
+     GEN9_PGCTL_SSB_EU210_ACK |
+     GEN9_PGCTL_SSB_EU311_ACK;
+
+ for (s = 0; s < s_max; s++) {
+ if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
+ /* skip disabled slice */
+ continue;
+
+ sseu->slice_mask |= BIT(s);
+ sseu->subslice_mask = info->sseu.subslice_mask;
+
+ for (ss = 0; ss < ss_max; ss++) {
+ unsigned int eu_cnt;
+
+ if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
+ /* skip disabled subslice */
+ continue;
+
+ eu_cnt = 2 * hweight32(eu_reg[2 * s + ss / 2] &
+       eu_mask[ss % 2]);
+ sseu->eu_total += eu_cnt;
+ sseu->eu_per_subslice = max_t(unsigned int,
+      sseu->eu_per_subslice,
+      eu_cnt);
+ }
+ }
+}
+
 static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
     struct sseu_dev_info *sseu)
 {
@@ -4483,7 +4538,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
 
  sseu->slice_mask |= BIT(s);
 
- if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv))
+ if (IS_GEN9_BC(dev_priv))
  sseu->subslice_mask =
  INTEL_INFO(dev_priv)->sseu.subslice_mask;
 
@@ -4589,8 +4644,10 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
  cherryview_sseu_device_status(dev_priv, &sseu);
  } else if (IS_BROADWELL(dev_priv)) {
  broadwell_sseu_device_status(dev_priv, &sseu);
- } else if (INTEL_GEN(dev_priv) >= 9) {
+ } else if (IS_GEN9(dev_priv)) {
  gen9_sseu_device_status(dev_priv, &sseu);
+ } else if (INTEL_GEN(dev_priv) >= 10) {
+ gen10_sseu_device_status(dev_priv, &sseu);
  }
 
  intel_runtime_pm_put(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 861b29f57c09..751ba401be8c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8037,11 +8037,18 @@ enum {
 #define   CHV_EU311_PG_ENABLE (1<<1)
 
 #define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice)*0x4)
+#define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \
+      ((slice) % 3) * 0x4)
 #define   GEN9_PGCTL_SLICE_ACK (1 << 0)
 #define   GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice)*2))
+#define   GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F)
 
 #define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice)*0x8)
+#define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \
+      ((slice) % 3) * 0x8)
 #define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice)*0x8)
+#define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \
+      ((slice) % 3) * 0x8)
 #define   GEN9_PGCTL_SSA_EU08_ACK (1 << 0)
 #define   GEN9_PGCTL_SSA_EU19_ACK (1 << 2)
 #define   GEN9_PGCTL_SSA_EU210_ACK (1 << 4)
--
2.15.1


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[PATCH 14/59] drm/i915/cnl: Remove unnecessary check in cnl_setup_private_ppat

Timo Aaltonen-6
In reply to this post by Timo Aaltonen-6
From: Michel Thierry <[hidden email]>

BugLink: http://bugs.launchpad.net/bugs/1757573

There is no need check if PPGTT is disabled because that not possible
in CNL. Execlists and GuC submission modes rely on at least aliasing
PPGTT and even intel_sanitize_enable_ppgtt says: "We don't allow disabling
PPGTT for gen9+ as it's a requirement for execlists, the sole mechanism
available to submit work."

Suggested-by: Daniele Ceraolo Spurio <[hidden email]>
Cc: Rodrigo Vivi <[hidden email]>
Signed-off-by: Michel Thierry <[hidden email]>
Reviewed-by: Daniele Ceraolo Spurio <[hidden email]>
Signed-off-by: Rodrigo Vivi <[hidden email]>
Link: https://patchwork.freedesktop.org/patch/msgid/20171027223207.7869-1-michel.thierry@...
(cherry picked from commit d9b99ffcb5aa113d175a3df845c72eac0d4624e0)
Signed-off-by: Timo Aaltonen <[hidden email]>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 2af65ecf2df8..1801c38a171d 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3171,12 +3171,6 @@ static void cnl_setup_private_ppat(struct intel_ppat *ppat)
  ppat->match = bdw_private_pat_match;
  ppat->clear_value = GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3);
 
- /* XXX: spec is unclear if this is still needed for CNL+ */
- if (!USES_PPGTT(ppat->i915)) {
- __alloc_ppat_entry(ppat, 0, GEN8_PPAT_UC);
- return;
- }
-
  __alloc_ppat_entry(ppat, 0, GEN8_PPAT_WB | GEN8_PPAT_LLC);
  __alloc_ppat_entry(ppat, 1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC);
  __alloc_ppat_entry(ppat, 2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC);
--
2.15.1


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[PATCH 15/59] drm/i915/cnl: Symmetric scalers for each pipe

Timo Aaltonen-6
In reply to this post by Timo Aaltonen-6
From: Mika Kahola <[hidden email]>

BugLink: http://bugs.launchpad.net/bugs/1757573

For Cannonlake the number of scalers for each pipe is 2. Let's increase
the number of scalers for pipe C.

v2: Use INTEL_GEN() instead of IS_CANNONLAKE()

Signed-off-by: Mika Kahola <[hidden email]>
Reviewed-by: Rodrigo Vivi <[hidden email]>
Signed-off-by: Rodrigo Vivi <[hidden email]>
Link: https://patchwork.freedesktop.org/patch/msgid/1509530930-24960-1-git-send-email-mika.kahola@...
(cherry picked from commit 6e7406db8c3a6998e84a605d3e1e04b166e795d1)
Signed-off-by: Timo Aaltonen <[hidden email]>
---
 drivers/gpu/drm/i915/intel_device_info.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 875d428ea75f..db03d179fc85 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -347,7 +347,10 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
  struct intel_device_info *info = mkwrite_device_info(dev_priv);
  enum pipe pipe;
 
- if (INTEL_GEN(dev_priv) >= 9) {
+ if (INTEL_GEN(dev_priv) >= 10) {
+ for_each_pipe(dev_priv, pipe)
+ info->num_scalers[pipe] = 2;
+ } else if (INTEL_GEN(dev_priv) == 9) {
  info->num_scalers[PIPE_A] = 2;
  info->num_scalers[PIPE_B] = 2;
  info->num_scalers[PIPE_C] = 1;
--
2.15.1


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[PATCH 16/59] drm/i915: Use fallback forcewake if primary ack missing

Timo Aaltonen-6
In reply to this post by Timo Aaltonen-6
From: Mika Kuoppala <[hidden email]>

BugLink: http://bugs.launchpad.net/bugs/1757573

There is a possibility on gen9 hardware to miss the forcewake ack
message. The recommended workaround is to use another free
bit and toggle it until original bit is successfully acknowledged.

Some future gen9 revs might or might not fix the underlying issue but
using fallback forcewake bit dance can be considered as harmless:
without the ack timeout we never reach the fallback bit forcewake.
Thus as of now we adopt a blanket approach for all gen9 and leave
the bypassing the fallback bit approach for future patches if
corresponding hw revisions do appear.

Commit 83e3337204b2 ("drm/i915: Increase maximum polling time to 50ms
for forcewake request/clear ack") did increase the forcewake timeout.
If the issue was a delayed ack, future work could include finding
a suitable timeout value both for primary ack and reserve toggle
to reduce the worst case latency.

v2: use bit 15, naming, comment (Chris), only wait fallback ack
v3: fix return on fallback, backoff after fallback write (Chris)
v4: udelay on first pass, grammar (Chris)
v4: s/reserve/fallback

References: HSDES #1604254524
References: https://bugs.freedesktop.org/show_bug.cgi?id=102051
Cc: Chris Wilson <[hidden email]>
Cc: Rodrigo Vivi <[hidden email]>
Cc: Tvrtko Ursulin <[hidden email]>
Cc: Joonas Lahtinen <[hidden email]>
Cc: Sagar Arun Kamble <[hidden email]>
Signed-off-by: Mika Kuoppala <[hidden email]>
Reviewed-by: Chris Wilson <[hidden email]>
Link: https://patchwork.freedesktop.org/patch/msgid/20171102094836.2506-1-mika.kuoppala@...
(cherry picked from commit 7130630323c562597191653560963e61c5bd0f57)
Signed-off-by: Timo Aaltonen <[hidden email]>
---
 drivers/gpu/drm/i915/i915_reg.h     |   5 +-
 drivers/gpu/drm/i915/intel_uncore.c | 137 +++++++++++++++++++++++++++++++++---
 2 files changed, 130 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 751ba401be8c..57ed23091c3c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7774,8 +7774,9 @@ enum {
 #define  FORCEWAKE_ACK_MEDIA_GEN9 _MMIO(0x0D88)
 #define  FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0x0D84)
 #define  FORCEWAKE_ACK_BLITTER_GEN9 _MMIO(0x130044)
-#define   FORCEWAKE_KERNEL 0x1
-#define   FORCEWAKE_USER 0x2
+#define   FORCEWAKE_KERNEL BIT(0)
+#define   FORCEWAKE_USER BIT(1)
+#define   FORCEWAKE_KERNEL_FALLBACK BIT(15)
 #define  FORCEWAKE_MT_ACK _MMIO(0x130040)
 #define  ECOBUS _MMIO(0xa180)
 #define    FORCEWAKE_MT_ENABLE (1<<5)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 8c2ce81f01c2..f73da9288178 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -69,17 +69,104 @@ fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d)
        HRTIMER_MODE_REL);
 }
 
+static inline int
+__wait_for_ack(const struct drm_i915_private *i915,
+       const struct intel_uncore_forcewake_domain *d,
+       const u32 ack,
+       const u32 value)
+{
+ return wait_for_atomic((__raw_i915_read32(i915, d->reg_ack) & ack) == value,
+       FORCEWAKE_ACK_TIMEOUT_MS);
+}
+
+static inline int
+wait_ack_clear(const struct drm_i915_private *i915,
+       const struct intel_uncore_forcewake_domain *d,
+       const u32 ack)
+{
+ return __wait_for_ack(i915, d, ack, 0);
+}
+
+static inline int
+wait_ack_set(const struct drm_i915_private *i915,
+     const struct intel_uncore_forcewake_domain *d,
+     const u32 ack)
+{
+ return __wait_for_ack(i915, d, ack, ack);
+}
+
 static inline void
 fw_domain_wait_ack_clear(const struct drm_i915_private *i915,
  const struct intel_uncore_forcewake_domain *d)
 {
- if (wait_for_atomic((__raw_i915_read32(i915, d->reg_ack) &
-     FORCEWAKE_KERNEL) == 0,
-    FORCEWAKE_ACK_TIMEOUT_MS))
+ if (wait_ack_clear(i915, d, FORCEWAKE_KERNEL))
  DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n",
   intel_uncore_forcewake_domain_to_str(d->id));
 }
 
+enum ack_type {
+ ACK_CLEAR = 0,
+ ACK_SET
+};
+
+static int
+fw_domain_wait_ack_with_fallback(const struct drm_i915_private *i915,
+ const struct intel_uncore_forcewake_domain *d,
+ const enum ack_type type)
+{
+ const u32 ack_bit = FORCEWAKE_KERNEL;
+ const u32 value = type == ACK_SET ? ack_bit : 0;
+ unsigned int pass;
+ bool ack_detected;
+
+ /*
+ * There is a possibility of driver's wake request colliding
+ * with hardware's own wake requests and that can cause
+ * hardware to not deliver the driver's ack message.
+ *
+ * Use a fallback bit toggle to kick the gpu state machine
+ * in the hope that the original ack will be delivered along with
+ * the fallback ack.
+ *
+ * This workaround is described in HSDES #1604254524
+ */
+
+ pass = 1;
+ do {
+ wait_ack_clear(i915, d, FORCEWAKE_KERNEL_FALLBACK);
+
+ __raw_i915_write32(i915, d->reg_set,
+   _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL_FALLBACK));
+ /* Give gt some time to relax before the polling frenzy */
+ udelay(10 * pass);
+ wait_ack_set(i915, d, FORCEWAKE_KERNEL_FALLBACK);
+
+ ack_detected = (__raw_i915_read32(i915, d->reg_ack) & ack_bit) == value;
+
+ __raw_i915_write32(i915, d->reg_set,
+   _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL_FALLBACK));
+ } while (!ack_detected && pass++ < 10);
+
+ DRM_DEBUG_DRIVER("%s had to use fallback to %s ack, 0x%x (passes %u)\n",
+ intel_uncore_forcewake_domain_to_str(d->id),
+ type == ACK_SET ? "set" : "clear",
+ __raw_i915_read32(i915, d->reg_ack),
+ pass);
+
+ return ack_detected ? 0 : -ETIMEDOUT;
+}
+
+static inline void
+fw_domain_wait_ack_clear_fallback(const struct drm_i915_private *i915,
+  const struct intel_uncore_forcewake_domain *d)
+{
+ if (likely(!wait_ack_clear(i915, d, FORCEWAKE_KERNEL)))
+ return;
+
+ if (fw_domain_wait_ack_with_fallback(i915, d, ACK_CLEAR))
+ fw_domain_wait_ack_clear(i915, d);
+}
+
 static inline void
 fw_domain_get(struct drm_i915_private *i915,
       const struct intel_uncore_forcewake_domain *d)
@@ -88,16 +175,25 @@ fw_domain_get(struct drm_i915_private *i915,
 }
 
 static inline void
-fw_domain_wait_ack(const struct drm_i915_private *i915,
-   const struct intel_uncore_forcewake_domain *d)
+fw_domain_wait_ack_set(const struct drm_i915_private *i915,
+       const struct intel_uncore_forcewake_domain *d)
 {
- if (wait_for_atomic((__raw_i915_read32(i915, d->reg_ack) &
-     FORCEWAKE_KERNEL),
-    FORCEWAKE_ACK_TIMEOUT_MS))
+ if (wait_ack_set(i915, d, FORCEWAKE_KERNEL))
  DRM_ERROR("%s: timed out waiting for forcewake ack request.\n",
   intel_uncore_forcewake_domain_to_str(d->id));
 }
 
+static inline void
+fw_domain_wait_ack_set_fallback(const struct drm_i915_private *i915,
+ const struct intel_uncore_forcewake_domain *d)
+{
+ if (likely(!wait_ack_set(i915, d, FORCEWAKE_KERNEL)))
+ return;
+
+ if (fw_domain_wait_ack_with_fallback(i915, d, ACK_SET))
+ fw_domain_wait_ack_set(i915, d);
+}
+
 static inline void
 fw_domain_put(const struct drm_i915_private *i915,
       const struct intel_uncore_forcewake_domain *d)
@@ -119,7 +215,27 @@ fw_domains_get(struct drm_i915_private *i915, enum forcewake_domains fw_domains)
  }
 
  for_each_fw_domain_masked(d, fw_domains, i915, tmp)
- fw_domain_wait_ack(i915, d);
+ fw_domain_wait_ack_set(i915, d);
+
+ i915->uncore.fw_domains_active |= fw_domains;
+}
+
+static void
+fw_domains_get_with_fallback(struct drm_i915_private *i915,
+     enum forcewake_domains fw_domains)
+{
+ struct intel_uncore_forcewake_domain *d;
+ unsigned int tmp;
+
+ GEM_BUG_ON(fw_domains & ~i915->uncore.fw_domains);
+
+ for_each_fw_domain_masked(d, fw_domains, i915, tmp) {
+ fw_domain_wait_ack_clear_fallback(i915, d);
+ fw_domain_get(i915, d);
+ }
+
+ for_each_fw_domain_masked(d, fw_domains, i915, tmp)
+ fw_domain_wait_ack_set_fallback(i915, d);
 
  i915->uncore.fw_domains_active |= fw_domains;
 }
@@ -1148,7 +1264,8 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
  }
 
  if (INTEL_GEN(dev_priv) >= 9) {
- dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
+ dev_priv->uncore.funcs.force_wake_get =
+ fw_domains_get_with_fallback;
  dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
  fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
        FORCEWAKE_RENDER_GEN9,
--
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[PATCH 17/59] drm/i915: Implement ReadHitWriteOnlyDisable.

Timo Aaltonen-6
In reply to this post by Timo Aaltonen-6
From: Rafael Antognolli <[hidden email]>

BugLink: http://bugs.launchpad.net/bugs/1757573

The workaround for this is described as:

"if RenderSurfaceState.Num_Multisamples > 1, disable RCC clock gating if
RenderSurfaceState.Num_Multisamples == 1, set 0x7010[14] = 1"

Further documentation in the internal bug referenced by the bspec
suggest that any of the above suggestions should suffice to fix the
issue. We are going with disabling RCC clock gating.

Unfortunately, what we are doing doesn't match the name of the
workaround, but at least it matches its description.

This change improves CNL stability by avoiding some of the hangs seen in
the platform.

v2: Only disable RCC clock gating.

Signed-off-by: Rafael Antognolli <[hidden email]>
Reviewed-by: Rodrigo Vivi <[hidden email]>
Signed-off-by: Rodrigo Vivi <[hidden email]>
Link: https://patchwork.freedesktop.org/patch/msgid/20171103183027.5051-1-rafael.antognolli@...
(cherry picked from commit 0a60797a0efbc495f514304d83eb289bb55990a6)
Signed-off-by: Timo Aaltonen <[hidden email]>
---
 drivers/gpu/drm/i915/i915_reg.h        | 1 +
 drivers/gpu/drm/i915/intel_engine_cs.c | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 57ed23091c3c..f7fb79d7b4a3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3834,6 +3834,7 @@ enum {
  */
 #define SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
 #define  SARBUNIT_CLKGATE_DIS (1 << 5)
+#define  RCCUNIT_CLKGATE_DIS (1 << 7)
 
 /*
  * Display engine regs
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 6074e04dc99f..f2736474f6a1 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1320,6 +1320,9 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
  WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_GPGPU_LEVEL_MASK,
     GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
 
+ /* ReadHitWriteOnlyDisable: cnl */
+ WA_SET_BIT_MASKED(SLICE_UNIT_LEVEL_CLKGATE, RCCUNIT_CLKGATE_DIS);
+
  /* WaEnablePreemptionGranularityControlByUMD:cnl */
  I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
    _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
--
2.15.1


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[PATCH 18/59] drm/i915: Unify SLICE_UNIT_LEVEL_CLKGATE w/a for cnl

Timo Aaltonen-6
In reply to this post by Timo Aaltonen-6
From: Chris Wilson <[hidden email]>

BugLink: http://bugs.launchpad.net/bugs/1757573

gem_workarounds reports that the SLICE_UNIT_LEVEL_CLKGATE write isn't
sticking. Commit 0a60797a0efb ("drm/i915: Implement
ReadHitWriteOnlyDisable.") presumes that SLICE_UNIT_LEVEL_CLKGATE is a
masked register in the context image, but commit 90007bca6162
("drm/i915/cnl: Introduce initial Cannonlake Workarounds.") lists it as
an ordering unmasked register. The masked write will be losing the
default settings if we trust the original commit. That gem_workarounds
reports the value is lost entirely is more worrying though -- but it
clearly suggests that it is not a masked register in the context image,
so unify both w/a to use the original rmw.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103705
Fixes: 0a60797a0efb ("drm/i915: Implement ReadHitWriteOnlyDisable.")
References: 90007bca6162 ("drm/i915/cnl: Introduce initial Cannonlake Workarounds.")
Signed-off-by: Chris Wilson <[hidden email]>
Cc: Rafael Antognolli <[hidden email]>
Cc: Rodrigo Vivi <[hidden email]>
Cc: Oscar Mateo <[hidden email]>
Cc: Mika Kuoppala <[hidden email]>
Cc: Jani Nikula <[hidden email]>
Cc: Joonas Lahtinen <[hidden email]>
Link: https://patchwork.freedesktop.org/patch/msgid/20171111100336.11020-1-chris@...
Reviewed-by: Rafael Antognolli <[hidden email]>
(backported from commit 34991bd48c927712678d0cea77628328f9046923)
Signed-off-by: Timo Aaltonen <[hidden email]>
---
 drivers/gpu/drm/i915/intel_engine_cs.c | 3 ---
 drivers/gpu/drm/i915/intel_pm.c        | 9 ++++++---
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index f2736474f6a1..6074e04dc99f 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1320,9 +1320,6 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
  WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_GPGPU_LEVEL_MASK,
     GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
 
- /* ReadHitWriteOnlyDisable: cnl */
- WA_SET_BIT_MASKED(SLICE_UNIT_LEVEL_CLKGATE, RCCUNIT_CLKGATE_DIS);
-
  /* WaEnablePreemptionGranularityControlByUMD:cnl */
  I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
    _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5c5667fbdb3d..e691cddaba88 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8519,6 +8519,7 @@ static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
 
 static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
 {
+ u32 val;
  cnp_init_clock_gating(dev_priv);
 
  /* This is not an Wa. Enable for better image quality */
@@ -8533,11 +8534,13 @@ static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
  I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
    DISP_FBC_MEMORY_WAKE);
 
+ val = I915_READ(SLICE_UNIT_LEVEL_CLKGATE);
+ /* ReadHitWriteOnlyDisable:cnl */
+ val |= RCCUNIT_CLKGATE_DIS;
  /* WaSarbUnitClockGatingDisable:cnl (pre-prod) */
  if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0))
- I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,
-   I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
-   SARBUNIT_CLKGATE_DIS);
+ val |= SARBUNIT_CLKGATE_DIS;
+ I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE, val);
 }
 
 static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)
--
2.15.1


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[PATCH 19/59] drm/i915/glk: Refactor handling of PLANE_COLOR_CTL for GLK+

Timo Aaltonen-6
In reply to this post by Timo Aaltonen-6
From: James Ausmus <[hidden email]>

BugLink: http://bugs.launchpad.net/bugs/1757573

Since GLK, some plane configuration settings have moved to the
PLANE_COLOR_CTL register. Refactor handling of the register to work like
PLANE_CTL. This also allows us to fix the set/read of the plane Alpha
Mode for GLK+.

v2: Adjust ordering of platform checks to be newest->oldest, drop
redundant comment about alpha blending. (Ville)

v3: Move Alpha Mode bits out of skl_plane_ctl_format into
skl_plane_ctl_alpha, and drop glk_plane_ctl_format, drop initialization
of state->color_ctl on platforms that don't use it, and drop color_ctl
local var. (Ville)

v4: Consolidate skl_plane_ctl_format switch statement on formats that
return the same settings. (Ville)

Signed-off-by: James Ausmus <[hidden email]>
Cc: Paulo Zanoni <[hidden email]>
Cc: Ville Syrjälä <[hidden email]>
Reviewed-by: Ville Syrjälä <[hidden email]>
Link: https://patchwork.freedesktop.org/patch/msgid/20171113181128.2926-1-james.ausmus@...
Signed-off-by: Ville Syrjälä <[hidden email]>
(cherry picked from commit 4036c78ccf6bf411d09dbf3ec9a9cc7c1838b7b2)
Signed-off-by: Timo Aaltonen <[hidden email]>
---
 drivers/gpu/drm/i915/i915_reg.h      | 12 ++++--
 drivers/gpu/drm/i915/intel_display.c | 73 ++++++++++++++++++++++++++++--------
 drivers/gpu/drm/i915/intel_drv.h     |  5 +++
 drivers/gpu/drm/i915/intel_sprite.c  | 11 +++---
 4 files changed, 76 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f7fb79d7b4a3..459e85d003e2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6261,7 +6261,7 @@ enum {
 #define _PLANE_CTL_2_A 0x70280
 #define _PLANE_CTL_3_A 0x70380
 #define   PLANE_CTL_ENABLE (1 << 31)
-#define   PLANE_CTL_PIPE_GAMMA_ENABLE (1 << 30)
+#define   PLANE_CTL_PIPE_GAMMA_ENABLE (1 << 30)   /* Pre-GLK */
 #define   PLANE_CTL_FORMAT_MASK (0xf << 24)
 #define   PLANE_CTL_FORMAT_YUV422 (  0 << 24)
 #define   PLANE_CTL_FORMAT_NV12 (  1 << 24)
@@ -6271,7 +6271,7 @@ enum {
 #define   PLANE_CTL_FORMAT_AYUV (  8 << 24)
 #define   PLANE_CTL_FORMAT_INDEXED ( 12 << 24)
 #define   PLANE_CTL_FORMAT_RGB_565 ( 14 << 24)
-#define   PLANE_CTL_PIPE_CSC_ENABLE (1 << 23)
+#define   PLANE_CTL_PIPE_CSC_ENABLE (1 << 23) /* Pre-GLK */
 #define   PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21)
 #define   PLANE_CTL_KEY_ENABLE_SOURCE (  1 << 21)
 #define   PLANE_CTL_KEY_ENABLE_DESTINATION (  2 << 21)
@@ -6284,13 +6284,13 @@ enum {
 #define   PLANE_CTL_YUV422_VYUY (  3 << 16)
 #define   PLANE_CTL_DECOMPRESSION_ENABLE (1 << 15)
 #define   PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14)
-#define   PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13)
+#define   PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13) /* Pre-GLK */
 #define   PLANE_CTL_TILED_MASK (0x7 << 10)
 #define   PLANE_CTL_TILED_LINEAR (  0 << 10)
 #define   PLANE_CTL_TILED_X (  1 << 10)
 #define   PLANE_CTL_TILED_Y (  4 << 10)
 #define   PLANE_CTL_TILED_YF (  5 << 10)
-#define   PLANE_CTL_ALPHA_MASK (0x3 << 4)
+#define   PLANE_CTL_ALPHA_MASK (0x3 << 4) /* Pre-GLK */
 #define   PLANE_CTL_ALPHA_DISABLE (  0 << 4)
 #define   PLANE_CTL_ALPHA_SW_PREMULTIPLY (  2 << 4)
 #define   PLANE_CTL_ALPHA_HW_PREMULTIPLY (  3 << 4)
@@ -6330,6 +6330,10 @@ enum {
 #define   PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30)
 #define   PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23)
 #define   PLANE_COLOR_PLANE_GAMMA_DISABLE (1 << 13)
+#define   PLANE_COLOR_ALPHA_MASK (0x3 << 4)
+#define   PLANE_COLOR_ALPHA_DISABLE (0 << 4)
+#define   PLANE_COLOR_ALPHA_SW_PREMULTIPLY (2 << 4)
+#define   PLANE_COLOR_ALPHA_HW_PREMULTIPLY (3 << 4)
 #define _PLANE_BUF_CFG_1_A 0x7027c
 #define _PLANE_BUF_CFG_2_A 0x7037c
 #define _PLANE_NV12_BUF_CFG_1_A 0x70278
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0c516d48e7bc..bd7118c8cb83 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3415,20 +3415,11 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
  case DRM_FORMAT_RGB565:
  return PLANE_CTL_FORMAT_RGB_565;
  case DRM_FORMAT_XBGR8888:
+ case DRM_FORMAT_ABGR8888:
  return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
  case DRM_FORMAT_XRGB8888:
- return PLANE_CTL_FORMAT_XRGB_8888;
- /*
- * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
- * to be already pre-multiplied. We need to add a knob (or a different
- * DRM_FORMAT) for user-space to configure that.
- */
- case DRM_FORMAT_ABGR8888:
- return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
- PLANE_CTL_ALPHA_SW_PREMULTIPLY;
  case DRM_FORMAT_ARGB8888:
- return PLANE_CTL_FORMAT_XRGB_8888 |
- PLANE_CTL_ALPHA_SW_PREMULTIPLY;
+ return PLANE_CTL_FORMAT_XRGB_8888;
  case DRM_FORMAT_XRGB2101010:
  return PLANE_CTL_FORMAT_XRGB_2101010;
  case DRM_FORMAT_XBGR2101010:
@@ -3448,6 +3439,33 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
  return 0;
 }
 
+/*
+ * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
+ * to be already pre-multiplied. We need to add a knob (or a different
+ * DRM_FORMAT) for user-space to configure that.
+ */
+static u32 skl_plane_ctl_alpha(uint32_t pixel_format)
+{
+ switch (pixel_format) {
+ case DRM_FORMAT_ABGR8888:
+ case DRM_FORMAT_ARGB8888:
+ return PLANE_CTL_ALPHA_SW_PREMULTIPLY;
+ default:
+ return PLANE_CTL_ALPHA_DISABLE;
+ }
+}
+
+static u32 glk_plane_color_ctl_alpha(uint32_t pixel_format)
+{
+ switch (pixel_format) {
+ case DRM_FORMAT_ABGR8888:
+ case DRM_FORMAT_ARGB8888:
+ return PLANE_COLOR_ALPHA_SW_PREMULTIPLY;
+ default:
+ return PLANE_COLOR_ALPHA_DISABLE;
+ }
+}
+
 static u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
 {
  switch (fb_modifier) {
@@ -3504,7 +3522,8 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
 
  plane_ctl = PLANE_CTL_ENABLE;
 
- if (!IS_GEMINILAKE(dev_priv) && !IS_CANNONLAKE(dev_priv)) {
+ if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
+ plane_ctl |= skl_plane_ctl_alpha(fb->format->format);
  plane_ctl |=
  PLANE_CTL_PIPE_GAMMA_ENABLE |
  PLANE_CTL_PIPE_CSC_ENABLE |
@@ -3523,6 +3542,20 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
  return plane_ctl;
 }
 
+u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state)
+{
+ const struct drm_framebuffer *fb = plane_state->base.fb;
+ u32 plane_color_ctl = 0;
+
+ plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
+ plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
+ plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
+ plane_color_ctl |= glk_plane_color_ctl_alpha(fb->format->format);
+
+ return plane_color_ctl;
+}
+
 static int
 __intel_display_resume(struct drm_device *dev,
        struct drm_atomic_state *state,
@@ -8413,7 +8446,7 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
 {
  struct drm_device *dev = crtc->base.dev;
  struct drm_i915_private *dev_priv = to_i915(dev);
- u32 val, base, offset, stride_mult, tiling;
+ u32 val, base, offset, stride_mult, tiling, alpha;
  int pipe = crtc->pipe;
  int fourcc, pixel_format;
  unsigned int aligned_height;
@@ -8435,9 +8468,16 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
  goto error;
 
  pixel_format = val & PLANE_CTL_FORMAT_MASK;
+
+ if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
+ alpha = I915_READ(PLANE_COLOR_CTL(pipe, 0));
+ alpha &= PLANE_COLOR_ALPHA_MASK;
+ } else {
+ alpha = val & PLANE_CTL_ALPHA_MASK;
+ }
+
  fourcc = skl_format_to_fourcc(pixel_format,
-      val & PLANE_CTL_ORDER_RGBX,
-      val & PLANE_CTL_ALPHA_MASK);
+      val & PLANE_CTL_ORDER_RGBX, alpha);
  fb->format = drm_format_info(fourcc);
 
  tiling = val & PLANE_CTL_TILED_MASK;
@@ -12857,6 +12897,9 @@ intel_check_primary_plane(struct intel_plane *plane,
  state->ctl = i9xx_plane_ctl(crtc_state, state);
  }
 
+ if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ state->color_ctl = glk_plane_color_ctl(crtc_state, state);
+
  return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index ec1d5e96aaf6..1280a0260a6d 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -422,6 +422,9 @@ struct intel_plane_state {
  /* plane control register */
  u32 ctl;
 
+ /* plane color control register */
+ u32 color_ctl;
+
  /*
  * scaler_id
  *    = -1 : not using a scaler
@@ -1503,6 +1506,8 @@ static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
  return i915_ggtt_offset(state->vma);
 }
 
+u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state);
 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
   const struct intel_plane_state *plane_state);
 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 4a8a5d918a83..5baa0023964e 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -263,13 +263,9 @@ skl_update_plane(struct intel_plane *plane,
 
  spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 
- if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
+ if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
  I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
-      PLANE_COLOR_PIPE_GAMMA_ENABLE |
-      PLANE_COLOR_PIPE_CSC_ENABLE |
-      PLANE_COLOR_PLANE_GAMMA_DISABLE);
- }
-
+      plane_state->color_ctl);
  if (key->flags) {
  I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
  I915_WRITE_FW(PLANE_KEYMAX(pipe, plane_id), key->max_value);
@@ -1056,6 +1052,9 @@ intel_check_sprite_plane(struct intel_plane *plane,
  state->ctl = g4x_sprite_ctl(crtc_state, state);
  }
 
+ if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+ state->color_ctl = glk_plane_color_ctl(crtc_state, state);
+
  return 0;
 }
 
--
2.15.1


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